Abstract—Traditional operational transconductance amplifier (OTA) optimizers decouple sizing from layout synthesis, leading to poor results under layout-induced parasitics—a problem exacerbated in FinFET nodes. This work proposes a hierarchical methodology for FinFET nodes that maintains self-consistency between schematic-level and postlayout design, leveraging a SPICE-calibrated gm/ID methodology that incorporates layout parasitics. Unlike machine-learning-based approaches that rely on heavy SPICE simulations and large datasets, our approach is computationally efficient and invokes SPICE sparingly. Ex- perimental results across four OTA topologies demonstrate that performance of the sized circuit is greatly degraded after layout (up to 44% in UGF, 17 dB in DC gain, and 22 dB in CMRR), yet the systematic, closed-loop use of correction factors with self- consistent gm/ID methodology enables recovery of postlayout performance and yields designs that meet specifications. The entire flow requires only 10–15 full SPICE simulations, enabling thorough exploration of design space for high-quality solutions