Reconfigurable Approximate Computing (RAC) is emerging as a crucial approach for designing adaptive digital systems, particularly as modern AI models require dynamic error tolerance during runtime. To address this need, there is a requirement for a runtime reconfigurable approximate circuit design methodology that demonstrates varying error and power levels. Some of the previous works proposed dynamic approximate circuits, accepting error levels as constraints and then optimizing power consumption for each power level. This work explores and compares various Multi-Objective Evolutionary Algorithms (MOEAs) that modify circuit netlists to generate Pareto-optimal solutions, strategically replacing wires with control gates to achieve significant power savings. While technology-independent, our method was validated on various benchmarks using the Predictive FinFET ASAP 7nm Regular Vt Typical Corner PDK. This paper demonstrates that our proposed method enables more flexible and informed configuration selection by leveraging the error–power trade-off, ultimately leading to more efficient design choices from pareto-front solutions. The framework is released as an open-source tool for the VLSI research community for further adoption.