In this work, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell is investigated using calibrated process and device simulations. The simulation framework incorporates both fabrication process modeling and electrical read/write operation analysis of the floating-body storage mechanism. By optimizing the polysilicon body thickness, the device achieves its best performance at Tpoly = 20 nm, exhibiting a sensing window of 14.48 μA/μm and a retention time of 781 ms.