Modern digital systems face diverse security threats, such as piracy, counterfeiting, and side-channel attacks, across different stages of the IC lifecycle. Addressing these threats individually increases design complexity, cost, and overhead, often forcing trade-offs against other critical design parameters. This paper presents CRISP, a unified, reconfigurable, and platform-agnostic infrastructure for hardware security primitives that consolidates three key features: (i) static entropy via a Physical Unclonable Function (PUF), (ii) dynamic entropy via a True Random Number Generator (TRNG), and (iii) secure access to scan-based Design-for-Test (DFT) into a single reconfigurable circuit-level fabric. CRISP integrates these security features within the augmented flip-flops, enabling distributed and flexible access to these primitives. The all-digital nature of CRISP primitives makes it amenable to automation and attractive for both ASIC and FPGA platforms. Experimental evaluation shows promising results with PUF achieving near-ideal inter-HD (49.45%) and Pearson Correlation Coefficient (-0.01) with Bit Error Rate (BER) less than or equal to 20%, while TRNG shows autocorrelation function (ACF) with 95% confidence and both pass all the NIST SP800-22 Randomness Tests. Fabricated on a 65nm test chip, CRISP demonstrates low area and power overheads of 0.071x10^6 F^2/bit and 11.82 fJ/bit, respectively, demonstrating its practical viability.