To protect Edge AI chiplet-based systems from various attacks, an emerging solution is developing a distributed network of on-package security monitors to oversee individual chiplets. These monitors can be implemented either as active elements integrated within the substrate or as dedicated security helper chiplets. Connected through a secure intra-package network, these components continuously observe communication among regular chiplets (e.g., CPU, GPU, accelerators) and memory. Additionally, the security chiplets can provide on-demand security services, such as trusted execution (TEE) and cryptographic operations, to the functional chiplets. To explore the feasibility, usefulness, and tradeoffs of such a design, we study the cost, power, and performance implications of using such a model by developing a new framework. Our analysis highlights the cost tradeoffs across different design strategies.