Rapid Single-Flux-Quantum (RSFQ) circuits, with their advantages of low power consumption and high frequency, are gradually emerging as a potential alternative to Complementary Metal-Oxide-Semiconductor circuits. However high operating frequency brings more complex timing matching challenges. To effectively reduce routing difficulty and improve the overall chip performance, the layout stage must fully consider the circuit's timing matching and optimize the maximum path length. However, existing methods struggle to adequately consider both of these key metrics simultaneously. In light of this, we propose a timing-aware placement algorithm for RSFQ circuits to optimize chip area, improve clock frequency, and reducing the timing matching difficulty during the routing stage. First, an initial placement is generated based on the logic stage of the cells and the number of pins on each cell. Then, a clock distribution method is proposed to minimize clock wirelength, which in turn reduces the total wirelength. Finally, during the detailed placement process, techniques such as a cell pool, projection mapping, and a multi-factor free movement method for cells are introduced to reasonably adjust the cell positions, further optimizing the placement results. Experimental results show that, compared to existing RSFQ placement algorithms, this algorithm achieves significant optimization in terms of total wirelength and maximum path length.