Assertion Checkers are widely used in pre-silicon verification to catch bugs early, e.g. in simulation and formal verification environment, saving time and costs. These assertion checkers in the form of properties can be also reused as hardware checkers to validate the correct behaviour of real hardware in-field. They enable detection of errors during runtime for errors that escaped the used verification approaches, e.g. for difficult to trigger corner cases in the hardware appearing under real world conditions. Additionally, errors introduced in manufacturing or due to hardware faults, e.g. caused through radiation or aging, can be detected with them. An advantage of using hardware checkers in post-silicon is they can be reused from pre-silicon assertion checkers, saving time and effort of creating them from scratch. Our work showcases the implementation of such checkers starting from their selection from pre-silicon properties and their optimization for use as checkers in hardware. Afterwards, we convert them into synthesizable hardware description language code and finally suggest of a new interface to integrate the checkers into a processor design. We demonstrate our work on a 32-bit RISC-V processor NS31A on a FPGA development board, the Arty-7 100T CSG324 Xilinx and show checker inclusion in hardware needs only very little additional area. On top of that, we also shows suitable software and hardware recovery methods when a checker is raised. This enables reliable hardware operation even in case of errors and prevents undesired behavior happening.