In this paper, we present a TCAD-based GGNMOS digital-twin for Electrostatic discharge (ESD) characterization using TLP testing. First, the virtual device is created by simulating the fabrication process of a 0.35μm CMOS technology. The device and physics models are then calibrated to lab measurements. Second, a one-at-a-time (OAT) sensitivity analysis is performed for various device/process parameters. In particular, the impact of device/process parameters on the trigger point, breakdown point and on-resistance were investigated. Statistical box plots are used to interpret the results of the sensitivity analysis. Finally, the OAT analysis is leveraged to perform targeted labeled dataset including all the failure modes w.r.t the ESD design window was generated. This proposed platform opens up possibilities for design and refinement of the ESD window while also accounting for process variation.