Modeling Endurance Degradation of VCM-based 1T1R ReRAM Cell for Circuit Simulations

Supriya Chakraborty1, Seyed Hossein Hashemi Shadmehri2, Thiago Santos Copetti2, Tobias Gemmeke2, Leticia Maria Bolzani Poehls3
1RWTH Aachen University, 2RWTH Aachen University, 3IHP - Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Germany


Abstract

Valence Change Mechanism (VCM)-based Resistive Random Access Memories (ReRAMs) have a wide application spectrum, but limited endurance compromises their reliability during lifetime. A precise model that can assess the degradation of these devices is needed to evaluate ReRAM's reliability before deploying them for real-world applications. In this context, an aging model based on write operations is proposed for a bipolar, filamentary, VCM-based 1T1R ReRAM cell. We demonstrate that the aging of the ReRAM device can be modeled with a relationship between the number of programming cycles and a physical parameter, representing the concentration of oxygen vacancy (Vo). Different aging behaviors are investigated by changing the minimum Vo with cycling. The aging behavior of the ReRAM device is simulated using a polynomial function. A case study is implemented by designing the 1T1R bit cell using 28nm CMOS technology and the JART VCM compact model. The obtained results include the combined degradation effect of the transistor and the ReRAM device. Experimental validation shows that the proposed model effectively captures the device's endurance.