Edge detection is a core operation in computer vision, providing compact boundary cues for segmentation, recognition, tracking, and navigation. This paper presents an inter-pixel binary edge-detection (IPBED) pixel array design that decides edge or no edge directly on pixel boundaries and evaluates the design in circuit and array-level simulation. Only rail-to-rail binary (edge or no edge) signals traverse the array and periphery, which reduces bandwidth, improves noise tolerance, and simplifies readout. Threshold placement is tunable at design time (through device sizing and material choice) and in real time (by timing control). A layout-level prototype in 65-nm CMOS achieves a 6.85-µm pixel pitch, which explicitly includes the pixel and processing circuitry. The power-delay-product is about 4.6 fJ per pixel (including processing circuitry). Monte Carlo analysis over 10,000 instances indicates robustness to device variation. To keep the design lightweight, we retain only vertical and horizontal neighbor comparisons. Even so, on-scene data show that the emitted edge maps agree with standard software detectors, with F1 ≈ 0.75-0.85 versus a morphology baseline, Sobel, Prewitt, and Canny. IPBED is intended as an application-specific sensor for edge-centric tasks.