This paper presents HDL-DFGen, a framework for automatically generating digital filter architectures in VHDL and Verilog. The tool supports fixed FIR filters, adaptive filters from the LMS family, and novel reconfigurable architectures capable of implementing multiple algorithms within a single circuit. By combining parameterizable templates and reusable libraries, HDL-DFGen allows designers to specify key requirements, such as filter length, precision of integer and fractional parts, filter type, and architectural configuration (parallel, semi-parallel, or sequential), and obtain complete hardware descriptions in seconds. The proposed framework significantly reduces the time and effort required to design complex VLSI architectures, thus favoring the development of dedicated circuits for signal processing applications. HDL-DFGen enables the creation of high-order filters with scalable performance while preserving area and power efficiency. Results demonstrate that the automatically generated architectures achieve competitive metrics regarding circuit complexity, power consumption, and processing throughput.