Emerging non-volatile multilevel cell (MLC) memories offer high density and exhibit ultra-low leakage power, making them ideal candidates over SRAM and DRAM for larger caches in modern processors. However, the asymmetric access latency/energy among the states in an MLC memory cell presents opportunities for memory design optimisations. This paper leverages this MLC state asymmetry to propose cache schemes that optimize the tag/data access latency and energy efficiency. We propose to map all tag bits to the MSB to enable the All Tag in One Read(ATOR) scheme, which reduces hit latency and miss penalty by consolidating tag lookup into a single step MSB read. To further improve hit latency and energy efficiency, we propose to eliminate the data latency by having a priority way data block and reading the data along with all tag bits in the ATOR scheme. On top of that, we enhance cache capacity by utilising unused LSB bits in the tag array to store an extra data block. Our evaluation shows that the proposed ATOR-S/ATOR-P/ATOR-P-E achieves an average 5.9%/9.2%/9.4% performance improvement(IPC) over the baseline design, respectively. Our evaluations also showcase further average performance(IPC) improvement of 12.7% due to the most recently used data's placement in the priority way over the baseline design. ATOR-S achieves 11.7% reduction in average energy delay product compared to the baseline design on SPEC 2017 benchmarks.