Hardware verification is a critical and increasingly complex stage in the design of modern integrated circuits. This paper presents AutoSim, a Python and YAML-driven framework developed to automate simulation workflows and regression testing for SystemVerilog-based designs. AutoSim offers a flexible and reusable infrastructure to manage test planning, execution, and coverage analysis across multiple simulators including VCS, Xcelium, and QuestaSim. Using a declarative configuration approach, AutoSim minimizes manual effort by providing a consistent environment for simulation and result collection. The framework supports both directed and constrained-random testing, integrating seamlessly with UVM-based testbenches. To illustrate its practical application, the verification of a UART IP block is used as a case study, demonstrating how AutoSim simplifies multi-tool regression runs and helps accelerate verification closure. This work contributes to scalable and maintainable hardware verification flows, addressing challenges of reproducibility and tool interoperability that are essential for collaborative silicon development.