This paper presents a 4 transistor eDRAM gain cell capable of performing both conventional memory read-write operations and content-addressable memory (CAM) operations within the same compact memory structure. The proposed design extends the conventional gain-cell topology by incorporating a bias-controlled evaluation mechanism that enables single-ended matchline detection while maintaining full read, write, and storage functionality. This dual-mode capability allows the same array to function as a high-density memory during read/write cycles and as an associative CAM during search operations, reducing transistor count compared to other architectures. The circuit is implemented in GlobalFoundries' 22 nm FD-SOI technology and simulated on a 128 × 128 array. Monte Carlo simulations with 1000 samples demonstrated consistent memory behavior and reliable match and mismatch detection under local process variations. These results confirm the robustness and scalability of the proposed 4T eDRAM architecture, high- lighting its potential for energy-efficient, high-density computing in machine-learning accelerators, neuromorphic processors, and edge-intelligence applications.