Spiking neural networks (SNNs) are a promising class of artificial intelligence architectures that emulate the temporal and event-driven behavior of biological neurons. Their sparse and asynchronous computation achieves superior energy efficiency compared to the conventional artificial neural networks. This paper presents an energy-efficient analog hardware implementation of SNNs with on-chip learning capability, designed to operate efficiently in power constrained environments such as edge devices. The proposed neuron is based on the leaky integrate-and-fire model, which enables biologically realistic temporal dynamics. Synaptic weight update is governed by spike timing-dependent plasticity, which provides local, unsupervised learning directly within the analog domain. The proposed design employs a fully event-driven, low-power analog architecture implemented in a commercially available 12 nm FinFET process, ensuring compatibility with modern fabrication technologies. Through novel circuits and optimization, the neuron achieves an energy efficiency of 78 fJ per spike, demonstrating capability to operate in power-constrained environments.