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Session 1A

1:00pm 3:10pm

TUESDAY, MARCH 19

Interconnect Extraction and Modeling

Rajendran Panda, Motorola

Sammy Lee, Numerical Technology

 

1:05pm

1A.1

Fabrication Technologies for Three-Dimensional Integrated Circuits (Invited), Rafael Reif, Massachusetts Institute of Technology, Cambridge, MA

1:30pm

1A.2

Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes, Vikram Jandhyaia, Yong Wang, Dipanjan Gope, Richard Shi, University of Washington, Seattle, WA

1:55pm

1A.3

Inductance Aware Interconnect Scaling, Kaustav Banerjee and Amit Mehrota1, Stanford University, Stanford, CA and 1University of Illinois, Urbana, IL

2:20pm

1A.4

Accurate Model of Metal-Insulator-Semiconductor Interconnects, Gaofeng Wang1, Xiaoning Qi2, Zhiping Yu3 and Robert W. Dutton3, 1Intpax, Inc., Cupertino, CA, 2Sun Microsystems, Palo Alto, CA, 3Stanford University, Stanford, CA

2:45pm

1A.5

Transition Aware Global Signaling (TAGS), Himanshu Kaul and Dennis Sylvester, University of Michigan, Ann Arbor, MI

 


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International Symposium on Quality of Electronic Design
Copyright 1998-2002 ISQED. All rights reserved.
Revised: December 25, 2001.