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Session 1C

1:00pm 3:10pm

Design for Test

Co-Chairs: 

George Alexiou, University of Patras, Greece

Jayashree Saxena, Texas Instruments

1:05pm

1C.1

Test Generation and Fault Modeling for Stress Testing (Invited), Robert C. Aitken, Agilent Technologies

1:30pm

1C.2

Extending the Viability of IDDQ Testing in the Deep Submicron Era, Y. Tsiatouhas, Th. Haniotakis1, D. Nikolos2, and A. Arapoyanni3, Integrated Systems Development S.A., Athens, Greece, 1Southern Illinois University, Carbondale, IL, 2University of Patras, Patras, Greece, and 3University of Athens, Athens, Greece

1:55pm

1C.3

Design of Reconfigurable Access Wrappers for Embedded Core Based SOC Test, Sandeep Koranne, Philips Research Laboratories, Endhoven, The Netherlands

2:20pm

1C.4

Testing of Analogue Circuits via (Standard) Digital Gates, Daniela De Venuto, Michael J. Ohletz1 and Bruno Ricco2, Politecnico di Bari, Bari, Italy, 1Alcatel Microelectronics, Zaventem, Belgium and 2Universita di Bologna, Bologna, Italy

2:45pm

1C.5

Automatic Test Program Generation from RT-Level Microprocessor Descriptions, F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero, Politecnico di Torino, Torino, Italy

 


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International Symposium on Quality of Electronic Design
Copyright 1998 ISQED. All rights reserved.
Revised: December 25, 2001.