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Session 2A

3:30pm 5:40pm

Design for Process Variations

Co-Chairs:

Lukas van Ginneken, Magna Design

Pranav Ashar, NEC Labs

3:35pm

2A-1

Impact Analysis of Process Variability on Clock Skew, Enrico Malavasi, Stefano Zanella, Min Cao, Julian Uschersohn, Mike Misheloff and Carlo Guardiani, PDF Solutions, Inc., San Jose, CA

4:00pm

2A-2

Statistical Methods for the Determination of Process Corners, Michael Kocher and Gerhard Rappitsch, austriamicrosystems AG, Premstatten, Austria

4:25pm

2A-3

Design Method and Automation of Comparator Generation for Flash A/D Converter, Daegyu Lee, Jincheol Yoo and Kyusun Choi, Pennsylvania State University, University Park, PA

4:50pm

2A-4

A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14m DRAM Generation and Beyond, Chul-Hong Park, Soo-Han Choi, Sang-Uhk Rhie, Dong-Hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo and Jeong-Taek Kong, Samsung Electronics Co., Ltd., Yongin City, Korea

5:15pm

2A-5

A Robust Digital Delay Line Architecture in a 0.13m CMOS Technology Node for Reduced Design and Process Sensitivities, Prasun Raha, John Wilson, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera and Baher Haroun, Texas Instruments, Dallas, TX

 


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International Symposium on Quality of Electronic Design
Copyright 1998 ISQED. All rights reserved.
Revised: December 25, 2001.