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Session 2B

3:30pm 5:40pm

Power, Signal and EMI Analysis and Optimization

Co-Chairs: 

Amit Narayan, EDA Consultant

Marco Casale-Rossi, STMicroelectonics

3:35pm

2B-1

Optimization of the Power/Ground Network Wire-and-Space Sizing Based on Sequential Newtork Simplex Algorithm, Ting-Yuan Wang, Charlie Chung-Ping Chen, University of Wisconsin, Madison, WI

4:00pm

2B-2

Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network, Geng Bai and Ibrahim N. Hajj1 University of Illinois, IL and 1American University of Beirut, Beirut, Lebanon

4:25pm

2B-3

An EMI-Noise Analysis on LSI Design with Impedance Estimation, Kenji Shimazaki, Shouzou Hirano and Hiroyuki Tsujikawa, Matsushita Electric Industrial Co., Ltd., Kyoto, Japan

4:50pm

2B-4

Chip Level Signal Integrity Analysis & Crosstalk Prediction Using Artificial Neural Nets, A. Ilumoka, University of Hartford, West Hartford, CT

5:15pm

2B-5

On the Use of Windows for Accurate Analysis of Package Interconnects, Wendemagegnehu T. Beyene and Xingchao Yuan, Rambus, Inc., Los Gatos, CA

 


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International Symposium on Quality of Electronic Design
Copyright 1998-2002 ISQED. All rights reserved.
Revised: December 25, 2001.