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Session 2C

3:30pm 5:40pm

Methods and Metrics for Design Quality

Co-Chairs: 

Tak Young, Monterey Design

Jay Michlin, Cadence Design

3:35pm

2C-1

Productivity Maximization in Real World Fabs (Invited), Dan Maynard, IBM, Essex Junction, VT

4:00pm

2C-2

A New Design Cost Model for the 2001 ITRS (Invited), Gary Smith, Dataquest, San Jose, CA

4:25pm

2C-3

Optimal Synchronization Energy Allocation for CMOS Integrated Systems, Martin Saint-Laurent, Simon S. Singh1, Madhavan Swaminathan2, James D. Meindl2, Intel Corp., Austin, TX, 1National Semiconductor Corp., Santa Clara, CA and 2Georgia Institute of Technology, Atlanta, GA

4:50pm

2C-4

Design, Manufacture and Test - Quality Cost Estimation, Jim Gilbert, David Johnson and Ian Bell, University of Hull, Hull, United Kingdom

5:15pm

2C-5

Measurement of Inherent Noise in EDA Tools, Andrew B. Kahng and Stefanus Mantik1, University of California at San Diego, La Jolla, CA and 1University of California, Los Angeles, CA

 


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International Symposium on Quality of Electronic Design
Copyright 1998 ISQED. All rights reserved.
Revised: December 25, 2001.