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Session 3B

1:00pm-3:10pm

Verification in Achieving Design Quality

Co-Chairs: 

Lech Jozwiak, University of Eindhoven, The Netherlands

Olivier Sentieys, ENSSAT, France

1:05pm

3B-1

Approaches for Mitigating the State Explosion Problem in Hardware Verification (Invited), Shaz Qadeer, Compaq Systems Research Center, Palo Alto, CA

1:30pm

3B-2

Behavioral IP Specification and Integration Framework for High-Level Design Reuse, Olivier Sentieys, Sebastien Pillement and Daniel Chillet, University of Rennes, Lannion France

1:55pm

3B-3

On the Relation Between SAT and BDDs for Equivalence Checking, Sherief Reda, Rolf Drechsler1 and Alex Orailoglu, University of California at San Diego, La Jolla, CA and 1University of Bremen, Bremen, Germany

2:20pm

3B-4

Integrated Inductors Modeling and Tools for Automatic Selection and Layout Generation, Jose Ramon Sendra-Sendra, Javier del Pinto, Antonio Hernandez, Antonio Nunez, Javier Hernandez, Jaime Aguilera1 and Andres Garcia-Alonso1, INCIDE, Canary S.L., and 1INCIDE S.A., San Sebastian, Spain

2:45pm

3B-5

Organization of a Microprocessor Design Process Using Internet-Based Interoperable Workflows, Nguyen Quang Trung, Artur Kokoszka, Krystyna Siekierska, Adam Pawlak, Dariusz Obrebski, and Norbert Lugowski, Institute of Electron Technology, Warsaw, Poland

 


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International Symposium on Quality of Electronic Design
Copyright 1998 ISQED. All rights reserved.
Revised: January 25, 2002.