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Session 4B

3:30pm 5:15pm

Advanced Device Technology Issues in Circuit Design

Co-Chairs: 

Ken Shepard, Columbia University

Chune-Sin Yeh, Celestry

3:35pm

4B-1

IBM SA-12 ASICs for the Thuraya Satellite Digital Signal Processor, (Invited) David A. Sunderland, Gary Duncan, Brad Rasmussen, Harry Nichols, Dan Kain, Larry Lee, Brian Clebowicz, Rick Hollis, Larry Wissel1, and Tad Wilder1, Boeing Satellite Systems and 1IBM, Essex Junction, VT

4:00pm

4B-2

Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD, Pin Su, Samuel K.H. Fung1, Weidong Liu, and Chenming Hu, University of California, Berkeley, CA and 1IBM, Hopewell Junction, NY

4:25pm

4B-3

High Performance Double-Gate Device Technology, Challenges and Opportunities (Invited), Meikei Ieong, IBM, Hopewell Junction, NY

4:50pm

4B-4

Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-Over-Gate Architecture, A.M. Ionescu, K. Banerjee1, V. Pott, R. Fritschi, C. Hilbert, Ph. Fluckiger, G.-A. Racine, Ph. Renaud and M. Declercq, Swiss Federal Institute of Technology, Lausanne, Switzerland and 1Stanford University, Stanford, CA

5:15pm

4B-5

Single Electronics - How it Works. How it's Used. How it's Simulated (Invited), Christoph Wasshuber, Texas Instruments, Dallas, TX

 


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International Symposium on Quality of Electronic Design
Copyright 1998-2002 ISQED. All rights reserved.
Revised: December 25, 2001.