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Session 4C

3:30pm 5:15pm

Design, Planning and Closure

Co-Chairs: 

Charlie Chen, University of Wisconsin

Eileen You, Broadcom

3:35pm

4C-1

Timing and Design Closure in Physical Design Flows (Invited), Olivier Coudert, Monterey Design, Sunnyvale, CA

4:00pm

4C-2

Architecture Power Performance Optimization (Invited), George Cai, Intel Corp., Austin, TX

4:25pm

4C-3

Formulate for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning, Nicholas Chia-Yuan Chang, Yao-Wen Chang and Iris Hui-Ru Jiang, National Chiao-Tung University, Hsinchu, Taiwan

4:50pm

4C-4

Hierarchical Front-End Physical Design Solution Drives Modified Hand-Off (Invited), Wei-Jin Dai and Ken Saito1, Silicon Perspective, Santa Clara, CA and 1Mitsubishi Electric Corp.

5:15pm

4C-5

Future SOC Design Challenges and Solutions (Invited), Ed Cheng, Synopsis, Mountain View, CA

 


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International Symposium on Quality of Electronic Design
Copyright 1998-2002 ISQED. All rights reserved.
Revised: December 25, 2001.