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Poster Session

12:30pm - 3:30pm

 

P-01

Synthesis of Selectively Clocked Skewed Logic Circuits, Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh and Kaushik Roy, Purdue University, West Lafayette, IN

 

P-02

Low Power VLSI Architecture of Viterbi Scorer for HMM-based Isolated Word Recognition, Bok-Gue Park, Koon-Shik Cho and Jun-Dong Cho, SungKyunKwan University, Kyunggi-do, Korea

 

P-03

On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects, Dinesh Pamunuwa and Hannu Tenhunen, Royal Institute of Technology, Kista, Sweden

 

P-04

A Comprehensive Layout Methodology and Layout-Specific Analyses for Three-Dimensional Integrated Circuits, Syed M. Alam, Donald E. Troxel and Carl V. Thompson, Massachusetts Institute of Technology, Cambridge, MA

 

P-05

Reliable Laser Programmable Gate Array Technology, Joseph B. Bernstein, Zhuo Gao, Ji Luo, Hu Huang and Wei Zhang, University of Maryland, College Park, MD

 

P-06

VC Rating and Quality Metrics:  Why Bother?, Pierre Bricaud, Mentor Graphics Corp., Sophia Antipolis, France

 

P-07

An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST, E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, University of Patras, Patras, Greece

 

P-08

An Integrated Tool for Analog Test Generation and Fault Simulation, Sule Ozev and Alex Orailoglu, University of California, San Diego, La Jolla, CA

 

P-09

A Hybrid BIST Architecture and its Optimization for SoC Testing, Gert Jervan, Zebo Peng, Raimund Ubar1, and Helena Krus1, Linkoping University, Linkoping, Sweden and 1Tallinn Technical University, Estonia

 

P-10

Native Mode Functional Self-Test Generation for Systems-on-Chip, Kamalanayan Jayaraman, Vivekananda M. Vedula and Jacob A. Abraham, University of Texas, Austin, TX

P-11

Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs), Mandeep Singh and Israel Koren, University of Massachusetts, MA

 

P-12

Human Immune System - Inspired Architecture for Self-Healing Digital Systems, P.K. Lala and B. Kiran Kumar, University of Arkansas, Fayetteville, AR

 

P-13

Impact of Low-K on Crosstalk, G. Serval, D. Deschacht, F. Saliou1, J.L. Mattei1, and F. Huret1, LIRRM, Montpellier, France and 1Universite de Bretagne, Brest, France

 

P-14

Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria, Amjad Hajjar and Tom Chen, Colorado State University, Fort Collins, CO

 

P-15

In Search of the Origin of VHDL's Delta Delays, Sumit Ghosh, Stevens Institute of Technology, Hoboken, NJ

 

P-16

Inductive Properties of Power Distribution Grids in High Speed Integrated Circuits, Andrey V. Mezhiba and Eby G. Friedman, University of Rochester, Rochester, NY

 

P-17

Characterizing the Current Degradation of Abnormally Structured MOS Transistors Using a 3D Poisson Solver, Jin-Kyu Park, Keun-Ho Lee, Chang-Sub Lee, Gi-Young Yang, Young-Kwan Park and Jeong-Taek Kong, Samsung Electronics, Co., Ltd., Yongin City, Korea

 

P-18

AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections, Tae-young Oh, Zhiping Yu and Robert W. Dutton, Center for Integrated Systems, Stanford, CA

 

P-19

ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process, Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, and Wen-Yu Lo1, National Chiao-Tung University, Hsinchu, Taiwan and 1Silicon Integrated Systems (SiS) Corp., Hsinchu, Taiwan

 

P-20

Design of ESD Protection Device Using Statistical Methods, Naoyuki Shigyo, Hirobumi Kawashima and Seiji Yasuda, Toshiba Corporation Semiconductor Company, Yokohama, Japan

 

P-21

Economic Analysis of a Stopping- Rule in Branch Coverage Testing, Mehmet Sahinoglu, Scott Glover, Troy State University, Montgomery, AL


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International Symposium on Quality of Electronic Design
Copyright 1998-2002 ISQED. All rights reserved.
Revised: March 01, 2002.