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Tutorial Track A*

 

Test Methodologies for Quality Designs

Chair and moderator: Yervant Zorian, Logicvision

 

 

Tutorial A1

08:30am 12:15pm

 

Design-for-Test Techniques for SoC Designs

 

Organizer:         Janusz Rajski, Mentor Graphics Corporation

Presenters:        Janusz Rajski, Mentor Graphics Corporation

Geir Eide, Mentor Graphics Corporation

 

This tutorial aims to jump start the designer to new levels of practical test expertise by presenting DFT methodologies, solutions, and technological advancements for addressing today's toughest DFT issues. The tutorial briefly introduces basic DFT concepts and techniques, and focuses on practical issues such as: IP core design guidelines that enable test reuse, DFT for complex SoC designs, embedded memory test, at-speed test, and DFT integration into the design flow. The tutorial presents in detail structural Design-for-Test methodologies based on scan, i.e. scan cell design, scan operation, scan chain optimization, multiple clock domains, test logic, test points, basic concepts of Logic BIST, Embedded Deterministic Test (EDT) and boundary scan. The highlights of the section addressing ATPG include: design rules checking, random and deterministic test pattern generation, pattern compression techniques, test pattern verification, combinational and sequential pattern types, at-speed test. Special section of the tutorial is devoted to testing of embedded memories. It reviews: memory types, fault models, test algorithms, and test methods (Memory BIST and Vector translation).

 

Tutorial A2

1:30pm 5:15pm

 

IDDx and Defect Based Testing

 

Organizer:         Sreejit Chakravarty, Intel Corporation

Presenters:        Sreejit Chakravarty, Intel Corporation

 

The shorter design cycle time to meet time to market, aggressive designs to meet performance targets in order to keep ahead of the competition etc. are resulting in a host of quality issues that the manufacturing community is faced with. For ASICS, the traditional approach of relying on structural testing and the classical s@ fault model leaves quality holes. For testing high-end processors, use of expensive functional testers is inevitable. This raises the question of how to ensure quality products while using low cost testers. Among many, two ideas are being explored by the test community viz. current based testing, referred to here as IDDx testing, and defect based testing. The commonality of these two distinct testing techniques is that both take into account the kind of defects that occur during manufacturing and proactively target them. Both can be used in conjunction with low cost structural testing. This tutorial provides an overview of these two important areas of test research that will only grow in importance with time.

 

* This tutorial is part of the IEEE Computer Society TTTC Test Technology Educational Program (TTEP) 2002.

 


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International Symposium on Quality of Electronic Design
Copyright 1998-2002 ISQED. All rights reserved.
Revised: December 25, 2001.