Sponsored by Ammocore & Ascend Design Automation
Evening Panel Discussion
Quality a Design Constraint for Sub 100nm Designs?
Chatterjee, President and CEO, SiliconMap, LLC
sub-micron design (below 100nm) present a number of new design challenges.
These include very high masking costs, new interconnect materials and parasitic
phenomenon, significant re-engineering at the device level due to changes in
basic device performance, very high gate count and pin count designs, complexity
in high pin count packaging & test, and finally reduced product life in the
marketplace do to the rapid rollout of new technologies. One of the trade
offs that is taking place in the industry to address these issues is the
decision toward “design existence”, which is the selection of the “first
functional implementation” of a design, over “design quality” which is the
selection of the “optimal implementation” of a design.
Callen Carpenter, President and CEO, Silicon Metrics Corp.
Monticelli, Fellow at National Semiconductor, Inc.
Paul Kempf, CTO and VP Engineering, Jazz Semiconductor, Inc
Resve Saleh, NSERC/PMC Sierra Chair, Professor, UBC Vancouver
John Kibarian, President and CEO, PDF Solutions, Inc.
Norm Towson, President and CEO, Netcell Corporation
Symposium on Quality of Electronic Design