ISQED05 Panel Discussion

Tuesday March 22, 2005

Session EP2

Panel Discussion & Dinner

Donner Pass Room

7:00pm -9:00pm

 

Breakthroughs and Barriers in Nanoelectronics - Can we build systems with nano devices?

 

Panel Organizer: Ali Keshavarzi, Intel

Panel Moderator: Michael Santarini - Sr. Tech Editor EDN Magazine

 

Scaling of CMOS technology continues in spite of tremendous technology development barriers, design challenges and prohibitive costs. Today, the 65nm CMOS technology node is moving from development to high volume manufacturing while research and development continues on future technology nodes including 45nm, 30nm and beyond. However, design of ICs in these scaled technologies faces growing limitations. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. These requirements pose several difficulties across a range of disciplines spanning technology, fabrication, transistor structure, circuits, systems, design, and architecture. On the technology front, the question arises whether we can continue to scale CMOS technology or whether we are close to the end of the ITRS roadmap. Should we continue along the traditional CMOS scaling path - reduce effective oxide thickness, improve channel mobility, and minimize parasitics - or consider a more radical departure from planar CMOS to non-planar device structures such as tri-gate and FinFET thin body transistors? Can we translate the device electrostatic improvement to performance gain? Should we begin to consider nanowires, nanotubes, and other novel nano molecular devices? If so, how important are self-assembly and bottom-up manufacturing in making future systems? By what means will we take the current charge-based electronics forward to its limit before turning to quantum computing and other revolutionary physics and more exotic ideas such as spintronics? On the design front, while researchers are exploring various circuit design techniques to deal with process variation and leakage, it is unclear how to optimize systems with non-planar CMOS devices and other novel nano devices. Do we need new circuit design methods? What are the implications for design community? The goal of nanotechnology research community is to make systems either directly from nano devices and circuits or to impact scaling of silicon CMOS technology using attributes of nanotechnology such as self-assembly and lower manufacturing cost.

 

Panelists:

Philip Wong - Stanford University and formerly IBM 

Kazuo Yano - Hitachi - Central Research Lab - Research manager 

Robert Doering - TI Fellow - nanotechnology 

Wilfried Haensch - IBM Yorktown - device and integration technology- Sr. Manager 

Shekhar Borkar - Intel Fellow - circuits 

Franz Kreupl - Infineon - Corporate Research Labs - nanoelectronics project manager 

Andre DeHon - Caltech
 

 


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