Session 1B

San Juan Room

10:30am - 12:05pm

High Level Power/Noise Reduction Techniques

Chairs:    Farzan Fallah, Fujitsu Laboratories of America

Norman Chang, Apache Design Solutions

10:30 am

Introduction

10:35am

1B.1       

Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis

Dongku Kang, Yiran Chen, Kaushik Roy, Purdue University

11:05am

1B.2       

Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor

Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman, IBM

11:35am

1B.3       

TFT-LCD Application Specific Low-Power SRAM Using Charge-Recycling Technique

Kee-Jong Kim, Chris H. Kim, Kaushik Roy, Purdue University

11:50am

1B.4       

Error Analysis for the Support of Robust Voltage Scaling

David Roberts*, Todd Austin*, David Blaauw*, Krisztian Flautner**, Trevor Mudge*, *University of Michigan, **ARM Ltd., UK