ISQED05

Tuesday March 22, 2005

Session 3C

San Martin Room

3:15pm - 5:15pm

 

Quality System Level Design and Synthesis

 

Chairs:    Lech Jozwiak, Eindhoven University of Technology, The Netherlands

Artur Chojnacki, PDF Solutions

 

3:15pm

Introduction

 

3:20pm

3C.1       

A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks

Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy, Purdue University

 

3:50pm

3C.2       

An ILP Formulation for Reliability-Oriented High-Level Synthesis

Suleyman Tosun*, Ozcan Ozturk**, Nazanin Mansouri*, Ercument Arvas*, Mahmut Kandemir**, Yuan Xie**,*Syracuse University, **Pennsylvania State University

 

4:20pm

3C.3       

Analysis of the Effect Of LUT Size on FPGA Area and Delay Using Theoretical Derivations

Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong, Xidian University, China

 

4:50pm

3C.4

Reliability-Centric Hardware/Software Co-Design

Suleyman Tosun*, Nazanin Mansouri*, Ercument Arvas*, Mahmut Kandemir**, Yuan Xie**, *Syracuse University, **Pennsylvania State University  

 


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