ISQED05

Tuesday March 22, 2005

Session 4B

San Juan Room

5:15pm 6:50pm

 

Leakage and Reliability Management

 

Chairs:    Panda Rajendran, Freescale Semiconductor

Seung H. Kang, Agere Systems

 

5:15pm

Introduction

 

5:20pm

4B.1       

Modeling and Analysis of Gate Leakage In Ultra-Thin Oxide Sub-50nm Double Gate Devices And Circuits

Saibal Mukhopadhyay*, Keunwoo Kim**, Jae-Joon Kim**, Shih-Hsien Lo**, Rajiv V. Joshi**, Ching-Te Chuang**, Kaushik Roy*, *Dept. Of ECE, Purdue University, **IBM T. J. Watson Research Center, Yorktown Heights

 

5:50pm

4B.2       

Design for Degradation: Cad Tools for Managing Transistor Degradation Mechanisms

G Ananth Somayaji, Gautam Kapila, Texas Instruments

 

6:20pm

4B.3

A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology

Puneet Gupta, Andrew B. Kahng, Puneet Sharma, University of California at San Diego

 

6:35pm

4B.4       

Analysis and Design of LVTSCR-Based EOS/ESD Protection Circuits for Burn-In Environment

O. Semenov, H. Sarbishaei, M. Sachdev, University of Waterloo  

 


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