ISQED05

Wednesday March 23, 2005

Session 6A

San Carlos Room

1:00pm - 3:05pm

 

Issues in Noise and Timing

 

Chairs:    Rajeev Murgai, Fujitsu Laboratories of America

Eileen You, Cadence Design Systems

 

1:00pm

Introduction

 

1:05pm

6A.1       

A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries

Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan, Texas Instruments

 

1:35pm

6A.2       

Sensitivity-Based Gate Delay Propagation in Static Timing Analysis

Shahin Nazarian*, Massoud Pedram*, Emre Tuncer**, Tao Lin**, *University of Southern California, **Magma Design Automation

 

2:05pm

6A.3       

Fast Decap Allocation Algorithm for Robust On-Chip Power Delivery

Zhenyu Qi*, Hang Li*, Sheldon X.-D. Tan*, Lifeng Wu**, Xianlong Hong***, *University of California Riverside, **Cadence, Yici Cai***, ***Tsinghua Univiversity, China

 

2:35pm

6A.4       

Clock trees: differential or single ended?

Deepak Sekar, Georgia Institute of Technology  

 


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