ISQED05

Wednesday March 23, 2005

Session 7A

San Carlos Room

3:30PM 5:35pm

 

Advances in Floor Planning

 

Chairs:    Marco Casale-Rossi, STMicroelectronics

Tanay Karnik, Intel

 

3:30pm

Introduction

 

3:35pm

7A.1       

Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers

Meng-Chiou Wu, Rung-Bin Lin, Yuan Ze University, Taiwan

 

4:05pm

7A.2       

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design

Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang, Tsinghua University, China

 

4:35pm

7A.3       

Wire Planning with Bounded Over-the-Block Wires

Hua Xiang, I-Min Liu, Martin D.F. Wong, IBM

 

5:05pm

7A.4

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Tsinghua University, China

 

5:20pm

7A.5

Thermal-Aware Floorplanning Using Genetic Algorithms

W. Hung, Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, M. J. Irwin, Penn State University  

 


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