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A Scalable Methodology for Analog & Mixed-Signal Verification

Session 4D

Wednesday March 24, 2010

10:30am–12 Noon

Room: San José

Shyam Rapaka, Synopsys
Tapan Halder, Synopsys

Traditional verification approaches for analog & mixed-signal designs do not scale well with increasing design complexity and product functionality. Full chip verification in the presence of analog components can be very slow, tedious, and difficult to maintain. In this tutorial, we focus on a scalable methodology for analog & mixed-signal verification that leverages advanced techniques used for verification of digital designs. Behavioral modeling using Verilog-AMS and SystemVerilog constructs will be presented. This tutorial addresses the several challenging issues that present road blocks for verification closure, and presents a methodology that promotes reuse and easy to maintain verification environment. Various strategies will be explored, for both top-down and bottom-up approaches, to develop a framework that can be shared across design teams, design stages, and product cycles.

 

 


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