ISQED Conference At-a-Glance
- Check out the complete Technical Program
Monday, March 22, 2010
| 9:00am–5:00pm |
Room: Monterey/Carmel Design Technologies and Opportunities in Nano-Scale Era: Beyond 32 nm Technology Energy Efficient Digital Circuit Design Alternate Memories SOC Verification 3-D CAD Design Microprocessor Architecture Impacts on Power |
| 12 Noon–12:50pm |
Tuesday, March 23, 2010
| 8:30am–10:15am |
Room: Fir/Oak Keynote Speeches by: Sponsored by Mentor Graphics Ramanan Thiagarajah, Sr. Director of Product and Test Engineering, Inphi Corp |
||||
| 10:15am-10:30am |
Morning Break | ||||
| 10:30am–12 Noon |
SRAM Design for Quality Room: Monterey |
Mixed Signal and Power Control Circuits Room: Carmel |
Guaranteeing Timing Performance Room: Santa Clara |
Analog Design For Reliability Room: San José |
|
| 12 Noon–1:30am |
Room: Fir/Oak) Annual ISQED Quality Award (IQ Award 2010) Sponsored by Synopsys Best Paper Awards Committee Recognition Awards |
||||
|
Test of the Future: Some Thoughts for the Next Decade Antun Domic, Senior VP & GM, Synopsys |
|||||
| 1:30pm–3:30pm |
Lithography & DFM Room: Monterey |
Power Aware Memory Design Room: Carmel |
Embedded Tutorial Field solvers for advanced analog and digital designs Room: Santa Clara |
Poster Papers Room: Donner |
Exhibits |
| 3:30pm–3:45pm |
Afternoon Break |
||||
| 3:45pm–5:45pm |
Variability: Design, Test, and Characterization Room: Monterey |
Emerging Device and Design Techniques Room: Carmel |
Power & Performance Issues in System-level Design Room: Santa Clara |
Poster Papers Room: Donner |
|
| 5:45pm–6:30pm |
Evening Break |
||||
| 6:30pm–8:30pm |
Room: Fir/Oak Long Life Cycle Design - Is It Really Different from Traditional CE? Sponsored by Mentor Graphics |
||||
Wednesday, March 24, 2010
| 8:30am–10:15am |
Room: Fir/Oak Keynote Speeches by: Krishna Yarlagadda, President & CEO, HelloSoft Aki Fujimura, CEO - D2S & eBeam Initiative Steve Glaser – VP Strategy & Planning - Cadence Design Systems |
|||
| 10:15am–10:30am |
Morning Break | |||
| 10:30am–12 Noon |
Parametric and delay test Room: Monterey |
Package & IC Co-Design Room: Carmel |
Embedded Tutorial Field Solver Solutions for System Level & RF Room: Santa Clara |
Embedded Tutorial A Scalable Methodology for Analog & Mixed-Signal Verification Room: San José |
| 12 Noon–1:30pm |
Lunch Break | |||
| 1:30pm–3:30pm |
Advances in Power Distribution, Placement and Routing Room: Monterey |
Aging Analysis & Mitigation Room: Carmel |
Test, Quality, Cost and Debug Room: Santa Clara |
System-level NoC, SoC and ASIC design Room: San José |
| 3:30pm–3:45pm |
Afternoon Break | |||
| 3:45pm–5:45pm |
Clocking Strategy for Modern Low Power Multi-Core and Structured ASICs Room: Monterey |
Modeling and Analysis of Temperature and Power Room: Carmel |
Fault Tolerant Design Room: Santa Clara |
Quality system level design Room: San José |