Tom Beckley, Senior Vice President, Research and Development, Custom IC and Signoff, Silicon Realization Group, Cadence Design Systems, Inc.
As process technology marches relentlessly forward producing multi-billion-transistor integrated circuits, there is much discussion about best design techniques and power consumption strategies in the digital community. But what does this mean for the custom and analog design worlds? Is 20nm the final frontier? How about 14nm? Are there insurmountable problems due to the exacting and power-hungry devices that make up the analog world? Well, the custom dinosaur isn’t extinct quite yet. Join this session to hear how circuit design, physical implementation, and verification are fusing into a new advanced-node methodology that copes with layout-dependent effects, complex interconnect rules, and lithography/colorization challenges so that custom and digital design can flourish together.
About Tom Beckley
Tom Beckley is senior vice president of research and development for custom IC and signoff in the Silicon Realization Group. His responsibilities include developing the Cadence Virtuoso® custom design platform; driving the simulation, extraction, physical verification, and DFM technologies; and managing the OpenAccess (OA) database and central architecture and technology (CAT) teams, which provide database technology, software platforms, widgets, formats, and subsystems. Tom joined Cadence in 2004 via the acquisition of Neolinear, where he served as President and CEO. Neolinear developed innovative auto-interactive and automated analog/RF tools and solutions for mixed-signal design. Prior to Neolinear, Tom was head of the Systems Division at Avant! Corporation. He came to Avant! through the acquisition of Xynetix Design Systems, the market leader in advanced IC packaging and systems-level virtual prototyping where he was President and CEO. Prior to Xynetix, Beckley held engineering and management positions at Harris Corporation and General Motors. Tom received his BS in mathematics and physics from Kalamazoo College and an MBA from Vanderbilt University.
Luigi Capodieci, Director DFM/CAD - R&D Fellow – GLOBALFOUNDRIES
The introduction of 28nm high-volume production for IC semiconductor devices will usher the era of “extreme low-k1” manufacturing, i.e. the unprecedented situation in the long history of the silicon technology roadmap, where computationally intensive (and EDA-driven) Design-Technology Co-Optimization will become the key enabler to a product success in terms of yield, time-to-market and profitability. This talk will provide a review and technical analysis of the methodological innovations in Design Enablement flows which are being introduced for early production at 28nm, particularly advanced DFM physical verification and DFM-aware router implementations. Rule-based, model-based and the newly released pattern-matching based hybrid verification, pioneered, industry-first, at GLOBALFOUNDRIES are prominent examples of these new enablement flows. DFM methodologies are complemented by a set of novel foundry-based flows identified as Design-Enabled Manufacturing (DEM). While DFM provides process awareness into the design cycle through accurately calibrated models and verification flows (DFM sign-off), DEM enables manufacturing/design co-optimization, using automated physical design analysis and characterization, which in turn drive process optimization, fine-tuned to specific customer product designs. The presentation will conclude with a preview of the “variability-challenge” intrinsic in the 20nm node and with an anticipation of the innovative EDA solutions which are currently being developed in the new Foundry-supported collaborative eco-system.
About Luigi Capodieci
Dr. Luigi Capodieci has been working on lithographic imaging and process simulations for more than 15 years, with applications to Optical Proximity Correction, Phase Shift Masks, Resolution Enhancement Technology and Design/Process Co-Optimization. At Advanced Micro Devices, in California, he pioneered the field of Design For Manufacturability (DFM) integrating physical design CAD flows with rigorous layout printability process modeling and novel verification algorithms. He is currently an Engineering R&D Fellow and the Director of DFM/CAD at GLOBALFOUNDRIES (www.globalfoundries.com), coordinating DFM R&D from 45 and 32/28nm, down to the next generations of 20 and 14nm technology nodes. Dr. Capodieci holds a Doctor degree in Electronic Engineering and Computer Science from the University of Bologna, Italy and a Ph.D. in Electrical Engineering, from the University of Wisconsin-Madison, where he worked at the Center for Nanotechnology (CNTech, formerly Center for X-Ray Lithography). Dr. Capodieci has authored and co-authored more than 35 journal and conference technical publications and is the principal inventor or co-inventor in more than 30 U.S. Patents. He is also an active member of the IEEE and ACM technical organizations.
Christophe Muller , Professor, Aix-Marseille University
Currently, the microelectronics industry faces new technological challenges to continue improving the performances of memory devices in terms of access time, storage capacity, endurance or data retention. The main issue to overcome is the downsizing of the memory cell necessary to embed an increasing number of elementary devices and the fulfillment of increasingly aggressive specifications from applications. Regardless of its NAND or NOR architecture, Flash technology still dominates the markets of non-volatile memories. Nevertheless, since the downscaling of the conventional floating gate appears ever more complicated below 22 nm technological node, opportunities are opened for alternative devices relying on resistive switching. As a result, emerging memory concepts are being explored to satisfy the growing needs for storage capacity, while complying with drastic applicative specifications (lower power consumption, smaller form factor, longer data retention, zero-defect products...). In addition, beside "conventional" standalone or embedded memories, resistive switching concepts pave the way towards design of innovative electronic functions such as field programmable gate array (FPGA) or logic devices (e.g. Flip Flop) in which non volatile memory cells are distributed.
Christophe Muller was born in Metz, France in 1970. He received the Ph.D. degree in 1996, from the University Joseph Fourier in Grenoble, France. His Ph.D. thesis was focused on fast oxygen ion conductors for application in gas sensors and solid oxide fuel cells. In 1998, he joined University of South Toulon Var (France) as Associate Professor for developing studies on bulk ferroelectrics and later on integrated ferroelectric thin films for memory applications (FRAM) in a close industrial partnership. He was nominated as Full Professor in 2003 and joined the Aix-Marseille University in Marseille in September 2007 as leader of the "Memories" team within Im2np (Institute Materials Microelectronics Nanosciences of Provence). Last five years, he contributed to several European projects focused on emerging non-volatile memory technologies (FRAM, MRAM, RRAM...) with a specific interest on programming physical mechanisms and reliability performances. After promoting partnership research activities on micro and nanoelectronics within the Carnot Institute STAR during three years, he is presently director of the doctoral school "Sciences for engineers".
Rich Goldman, Vice President, Corporate Marketing & Strategic Alliances, Synopsys
This keynote examines the close linkage between the development of the semiconductor and space industries from the '50s to the present, and juxtaposes the incredible advances of computing power enabled by the semiconductor industry, and the amazing achievements of the manned space program utilizing such tiny computing power. In this insightful retrospective, Rich will explore how the achievements of both innovative industries have paved the way for astounding new technology and quality advances. Rich will also offer a glimpse into the future of what may change the way we inhabit our own world and travel beyond it.
About Rich Goldman
Rich Goldman is the Vice President of Corporate Marketing and Strategic Alliances for Synopsys and CEO of Synopsys Armenia, which was recently designated as a finalist for the ACE Award by the US Department of State. Rich holds BSCS from Syracuse University, MBA and MS Engineering Management from University of Dallas, and Honorary PhD from the State Engineering University of Armenia.
Dean Tullsen , Dept of Computer Science and Engineering UC San Diego
Moore's Law is not done yet. We continue to get more transistors to work with in each processor generation. Traditionally, these transistors have translated directly into performance gains. However, two phenomena have the potential to seriously derail that performance scaling, even in the face of increased transistor counts: the parallelism crisis and the power crisis. We'll talk about each phenomenon, why we need to address these at every level, from software down to circuits. We'll talk in particular about what we have been doing to address these issues, especially the parallelism crisis, in our group -- at the architecture, compiler, and programming language levels.
About Dean Tullsen
Dean Tullsen is a professor in the computer science and engineering department at UCSD. He received his PhD from the University of Washington in 1996, where he introduced the concept of simultaneous multithreading (hyper-threading). He has continued to work in the area of computer architecture and back-end compilation, where with various co-authors he has introduced several new ideas to the research community, including threaded multipath execution, symbiotic job scheduling for multithreaded processors, dynamic critical path prediction, speculative precomputation, heterogeneous multi-core architectures, conjoined core architectures, and event-driven simultaneous code optimization. He is a Fellow of the ACM and the IEEE.
Jos Huisken , Principal Scientist , Imec Netherlands / Holst Centre, Eindhoven, The Netherlands
A key challenge of wireless sensor nodes for personal health is their energy efficient design. Comparing to the design for mobile appliances, where performance is still a main driver to enable more features, in sensor nodes the energy efficiency is the prime objective. The field of wireless sensor nodes, in which we consider personal health monitoring as a representative example, may become the next development wave fuelling the semiconductor industry. Currently a lot of research is carried out to conceptualize such systems, where integration is a real challenge and not just an "engineering activity", especially for very small form factor sensor nodes using an energy harvester. While looking at the digital design, creating an energy-efficient architecture remains a challenge. However, in the quest for energy-efficient small ubiquitous wireless sensor nodes, low operating voltages are required. When reaching near-, or sub-threshold supply voltages performance becomes more unpredictable for instance due to variations in the manufacturing process and noise. Does this still allow us to use modern technologies for a high volume production of wireless sensor node ICs?
About Jos Huisken
Jos Huisken is a Principal Scientist at Holst Centre / IMEC Netherlands, responsible for the strategy and long-term research. In 1984 Jos Huisken joined Philips Research, after graduation on digital signal processor design from University of Twente, The Netherlands. Since then he has been involved in architectural synthesis for digital signal processors and applied these techniques for the first Digital Audio Broadcast (ETSI-DAB) IC's in the nineties. Subsequently, he has been involved in low power design from the architectural point of view. After investigating turbo and LDPC decoders, and being involved in creation of a spinout company from Philips, in 2008 he joined Holst Centre / IMEC Netherlands to work on ultra low power DSPs for wireless sensor nodes, specifically, for the body area networks, with a strong focus on low-voltage and low-power circuit design. Jos serves as reviewer for several journals, served as guest editor for IEEE Journal of Solid State Circuits, and served on program committees for DATE, DAC, ESSCIRC, ISSCC, and several smaller workshops and conferences. He owns about 10 patents, (co-)authored over 60 publications, and has given invited lectures at several universities, ISSCC, and several IEEE workshops.
Venu Menon , Vice President, Analog Technology Development, Technology and Manufacturing Group, Texas Instruments
Every electronic product in the world has analog semiconductor content and this content is growing in areas such as wireless communications, medicine, energy, transportation and security. Because analog chips have diverse and differentiated performance and power specifications, manufacturing technologies have to be tuned to meet these requirements. In this talk we will discuss some of the end market trends and the requirements they drive in analog technology development and manufacturing.
About Venu Menon
With more than twenty years of semiconductor experience, Venu continues to look at new ways to innovate and drive technology forward. As the vice president of TI’s Analog Technology Development organization, Venu manages the development of analog process technologies that support TI’s broad portfolio of analog products now and well into the future. A TIer for fifteen years, Venu has been involved in the continuous evolution of semiconductor technology. Prior to his current position, Venu served as the vice president of TI’s advanced CMOS1 development organization, leading the development of 130 and 65 nanometer process technologies. Before TI, Venu worked at SEMATECH in several functions and eventually served as the Director for Materials and Bulk Processes. He later served on the board at SEMATECH. Venu earned a PhD in Chemical Engineering from the Illinois Institute of Technology and holds an undergraduate degree from the University Institute of Chemical Technology in Mumbai, India.