Steering/Advisory Committee|Conference Committee|Technical Committee

Technical  Program Committee

Siva G. Narendra, Intel  (Chair)*

George P. Alexiou, University of Patras and Computer Technology Institute, Patras, Greece (Vice Chair)*




EDA Tools, Flows & IP Blocks; Interoperability and Implications (EDA)


EDA tools addressing design quality. EDA tools interoperability issues and implications. Management of design process, and design database. Effect of emerging processes & devices on design flows, tools, and tool interoperability. Emerging EDA standards. EDA design methodologies and tools that address issues which impact the quality of the realization of designs into physical integrated circuits. Tools and methods for comparison of libraries and hard IP blocks. Challenges and solutions of the integration, testing, and qualifying of multiple IP blocks. IP authoring tools and methodologies. Methods and tools for design and maintenance of technology independent hard and soft IP blocks. IP modeling and abstraction. Risk management of IP reuse. Third party testing of IP blocks.

  • Tom Chen, Hewlett-Packard (Chair)*

  • James Lei, Altera (Co-Chair)*

  • Olivier Sentieys, ENSSAT/IRISA, France*

  • Vamsi Srikantam, Agilent*

  • Antonio Nunez, University of Las Palmas, Spain*

  • Justin E. Harlow III, SRC*

  • Miodrag Potkonjak, UCLA*

  • Jay Michlin, Transitive Ltd., UK

  • Lech Jozwiak, Eindhoven University, Netherlands*

  • Mely Chen Chi, CYC University, Taiwan

  • Kris Verma, Seagate*

  • Pranav Ashar, NEC Lab*

  • Armita Peymandoust, Synopsys*

Design for Manufacturability & Quality (DFMQ) 


Analysis, modeling, and abstraction of manufacturing process parameters and effects for highly predictable silicon performance. Design and synthesis of high complexity ICs: signal integrity, transmission line effects, OPC, phase shifting, and sub-wavelength lithography, manufacturing yield and technology capability. Design for diagnosability, defect detection and tolerance; self-diagnosis, calibration and repair. Design and manufacturabilty issues for Digital, analog, mixed signal, RF, MEMS, opto-electronic, biochemical-electronic, and nanotechnology based ICs. Redundency and other yield improving techniques. Design quality definitions and standards; design quality metrics to track and assess the quality of electronic circuit design, as well as the quality of the design process itself; design quality assurance techniques. Global, social, and economic implications of design quality. Design metrics, methodologies and flows for custom, semi-custom, ASIC, FPGA, RF, memory, networking circuit, etc. with emphasis on quality. Design metrics and quality standards for SoC, and SiP.



  • Sani Nassif, IBM (Chair)*

  • Sarma B. K. Vrudhula, University of Arizona, Tuscon*

  • Tuna Tarim, Texas Instruments*

  • Gareth Keane, PMC-Sierra Inc.*

  • Charlie Chung-Ping Chen, National Taiwan University*

  • Enrico Malavasi, PDF Solutions*

  • Jeong-Taek Kong, Samsung*

  • Don Cottrell, Si2*

  • Sharad Saxena, PDF Solutions*

  • Vinod Malhotra, Synopsys*

  • Hirokazu Yonezawa, Panasonic* 

  • Chune-Sin Yeh, Cadence*

  • Kenneth Weng, TSMC*

  • Rolf Kraemer, IHP, Germany*

Package - IC Interaction & Co-Design (PDI)


Concurrent circuit and package design and effect on quality. Packaging electrical and thermal modeling and simulation for improved quality of product. SoC versus system in a package (SiP): design and technology solutions and tradeoffs; MCM and other packaging techniques; heat sink technology.

  • Ravi Mahajan, Intel (Chair)*

  • Erwin Cohen, IBM*

  • Madhavan Swaminathan, Georgia Tech 

  • Chris Ooi, OSE

  • Rao Tummala, Georgia Tech

  • Paul Wesling, HP

Design Verification and Design for Testability (DFVT)


Hardware and Software, formal and simulation based design verification techniques to ensure the functional correctness of hardware early in the design cycle. DFT and BIST for digital and SoC. DFT for analog/mixed-signal ICs and systems-on-chip, DFT/BIST for memories. Test synthesis and synthesis for testability. DFT economics, DFT case studies. DFT and ATE. Fault diagnosis, IDDQ test, novel test methods, effectiveness of test methods, fault models and ATPG, and DPPM prediction. SoC/IP testing strategies.

  • Li-C Wang, University of Santa Barbara (Chair)*

  • George Alexiou, University of Patras and Research Academic Computer Technology Institute (RA-CTI)*

  • T. W. Williams, Synopsys*

  •  Jacob Abraham, University of Texas, Austin*

  • Sreejit Chakravarty, Intel Corporation*

  • Marcel Jacomet, Univ. of Applied Sciences Berne (Berner FH), Switzerland*

  • Kwang-Ting (Tim) Cheng, Univ. of Californian, Santa Barbara*

  • Daniela De Venuto, Polytechnic of Bari*

  • David Bonyuet, Delta Search Labs*

  • Raimund Ubar, Tallinn Technical University, Estonia*  

  • Justin E. Harlow III, SRC*

  • Jayashree Saxena, Texas Instruments*

  • Matteo Sonza Reorda, Politecnico di Torino, Italy*

  • K. C. Chen, Cadence*

Robust Device, Interconnect, and Circuits (RDIC)


Device, substrate, interconnect, circuit , and IP block modeling and simulation techniques; quality metrics, model order reduction; CMOS, Bipolar, and SiGe HBTs device modeling in the context of advanced digital, RF and high-speed circuits. Modeling and simulation of novel device and interconnect concepts. Signal integrity analysis: coupling, inductive and charge sharing noise; noise avoidance techniques. Power grid design, analysis and optimization; timing analysis and optimization; thermal analysis and design techniques for thermal management. Modeling statistical process variations to improve design margin and robustness, use of statistical circuit simulators. Power-conscious design methodologies and tools; low power devices, circuits and systems; power-aware computing and communication;  system-level power optimization and management. Design techniques for leakage current management.

  • Amit Mehrotra, University of Illinois, Urbana (Chair)*

  • Jayasimha Prasad, Maxim*

  • Naehyuck Chang, Seoul National University*

  • Rajendran Panda, Motorola*

  • Samar Saha, Silicon Storage Technology*

  • Farzan Fallah, Fujitsu Labs of America*

  • Ram Krishnamurthy, Intel Corporation*

  • Sarma Vrudhula, University of Arizona*

  • Narain Arora, Cadence*

  • Norman Chang, Apache Solutions*

  • Payam Heydari, UC-Irvine*

  • Aswin Mehta, TI*

  • Jun Dong Cho, Sungkyunkwan University, Korea*

  • Lei Hei, UCLA*

  • Rajiv Joshi, IBM*

Effect of Technology on IC Design, Performance, Reliability, and Yield (TRD)


Effect of emerging processes & devices on designís time to market, yield, reliability, and quality. Emerging issues in DSM CMOS: e.g. sub-threshold leakage, gate leakage, technology road mapping and technology extrapolation techniques. New and novel technologies such as SOI, Double-Gate(DG)-MOSFET, Gate-All-Around (GAA)-MOSFET, Vertical-MOSFET, strained CMOS, high-bandwidth metallization, etc. Challenges of mixed-signal design in digital CMOS or BiCMOS technology, including issues of substrate coupling, cross-talk and power supply noise. Significance of reliability effects such as gate oxide integrity, electromigration, ESD, etc., in relation to electronic design. Impacts of process technologies on circuit design and capabilities (e.g. low-Vt transistors versus increased off-state leakages) and the accuracy, use and implementation of SPICE models that faithfully reflect process technologies. Successful applications of TCAD to circuit design.

  • Adrian Ionescu, EPFL (Chair)*

  • Steven H. Voldman, IBM*

  • Siva Narendra, Intel Corporation*

  • David Overhauser, Cadence*

  • Prasun Raha, TI*

  • Farid Najm, University of Toronto*

  • Michael Reinhardt, RUBICAD*

  • Jacques Gautier, LETI CEA, France*

  • Florin Udrea, University of Cambridge, England*

  • Ming-Dou Ker, National Chiao-Tung University, Taiwan*
Physical Design Tools & Methodologies (PDM)


Physical synthesis flows for correct-by-construction quality silicon, implementation of large SoC designs. Tool frameworks and datamodels for tightly integrated incremental synthesis, placement, routing, timing analysis and verification. Placement, optimization, and routing techniques for noise sensitivity reduction and fixing. Algorithms and flows for harnessing crosstalk-delay during physical synthesis. Tool flows and techniques for antenna rule and electromigration rule avoidance and fixing. Spare-cell strategies for ECO, decoupling capacitance and antenna rule fixing. Planning tools for predictable high-current, low-voltage power distribution. Reliable clock tree generation and clock distribution methodologies for Gigahertz designs. EDA tools, design techniques, and methodologies, dealing with issues such as: timing closure, R, L, C extraction, ground/Vdd bounce, signal noise/cross-talk /substrate noise, voltage drop, power rail integrity, electromigration, hot carriers, EOS/ESD, plasma induced damage and other yield limiting effects, high frequency effects, thermal effects, power estimation, EMI/EMC, proximity correction & phase shift methods, verification (layout, circuit, function, etc.).

  • Noel Menezes, Intel (Chair)*

  • Charlie Chung-Ping Chen, University of Wisconsin*

  • Jane Wang, Cadence Taiwan*

  • Howard Chen, IBM*

  • Eileen You, Cadence*

  • Tanay Karnik, Intel*

  • Marco Casale-Rossi, STMicroelectronics*

  • Michael Reinhardt, RUBICAD*

  • Rajeev Murgai, Fujitsu Laboratories of America*

  • Janet Meiling, Arizona State University*

  • Patrick Groeneveld, Eindhoven University of Technology, Netherlands*

  • Mohammad Mortazavi, Cadence*

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