International Symposium on Quality Electronic Design (ISQED)

ISQED2014 Tutorials


Monday, March 3, 2014
Great America Meeting Room 3

Best Design Practices for Modern Integrated Circuits

Chair & Moderator:
Prof. Arijit Raychowdhury - Georgia Institute of Technology

Prof. Suman Datta - Pennsylvania State University
Dr. Carlos Tokunaga - Intel Corporation
Prof. Sudhakar Yalamanchili - Georgia Institute of Technology
Prof. David D. Wentzloff , University of Michigan
Prof. Hua Wang - Georgia Institute of Technology
Prof. Sayeef Salahuddin - University of California at Berkeley

Tutorial 1

Past, Present and Future of High Performance Logic Transistors

Prof. Suman Datta, Pennsylvania State University

Summary: Energy efficient CMOS technology scaling per Moore's law demands a) continued electrostatic improvement; c) channel transport enhancement and, likely, c) new switching mechanism Strained silicon channel and high-k/metal gate stacks have enabled CMOS technology scaling for the past decade. With no room left for further scaling of the gate oxide thickness or junction engineering, the device community is left only with scaling of body thicknesses of field effect transistors to improve electrostatics. We will present state of the art and future FinFET technologies where silicon fins are likely to be replaced with Germanium, compound semiconductor (III-V) materials and their heterostructures. The impact of fin thickness scaling and quantum mechanical confinement on the electrostatics, performance and variation in such devices will be presented and its implication for super threshold and near threshold computing. Further scaling of supply voltage requires new switching mechanism like band to band tunneling for high ON current and sub-thermal switching slope devices. We will discuss recent progress on compound semiconductor based Tunnel FETs (TFETs) and their impact on energy-delay performance of logic and memory circuits. We will present a holistic device-circuit-system design strategy to take advantage of TFET device technology. Very recently, two-dimensional (2D) layered transition metal dichalcogenide materials (MX2) (M = Mo, W; X = S, Se, Te) have recently emerged as alternatives to III-Vs as channel materials for CMOS devices. Due to the very low value of the characteristic screening length (λ), these MX2 may give advantages over traditional 3D semiconductors for future tunnel field effect transistor applications.

About Prof. Suman Datta
Dr. Datta joined Penn State with a joint appointment in Electrical Engineering and the Materials Research Institute in 2007. Prior to joining Penn State, he was a Principal Engineer in the Advanced Transistor and Nanotechnology Group at Intel Corporation. He held the Joseph Monkowski Professorship for Early Faculty Career Development. He is exploring new materials, novel nanofabrication techniques, new classical and non-classical device structures for CMOS "enhancement" and CMOS "replacement" for future energy efficient, high performance and information processing systems. He is also interested in exploring novel energy conversion devices harnessing nanoscale properties of nanostructures. He has published over 140 journal and conference articles and holds 145 US and international patents related to advanced process technologies and transistor architecture. He is an IEEE fellow and a distinguished lecturer of the IEEE Electron Devices Society.

Tutorial 2

Integrated Techniques for Variation-Tolerant, Energy-Efficient Circuits

Dr. Carlos Tokunaga, Intel Corporation

Summary: The demand for high-performance operation in extremely power-constrained platforms such as smartphones and tablets requires architecture and circuit techniques that scale from efficient operation at low voltage to high performance when needed. It is well-known that energy efficiency improves as supply voltage is scaled down. Achieving this voltage reduction requires techniques that address intrinsic VMIN limitations in arrays (SRAM, register file arrays, ROMs),voltage, temperature and reliability guardband reduction, as well as techniques for reducing leakage energy. It is important that these techniques, while providing energy-efficient operation at low voltage, do not impact high performance mode which can be critical for many compute-intensive workloads. This tutorial will explore design techniques used to achieve energy-efficiency and resiliency to variations and discuss the challenges of integrating these techniques in an SoC. Recent results will be presented from several general-purpose processor and graphics test chips.

About Dr. Carlos Tokunaga
Carlos Tokunaga received the B.S. degree in electronics engineering from the University of Los Andes, Bogota, Colombia, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 2005 and 2008 respectively. He is currently a Research Scientist at the Circuit Research Lab, Intel. His research interests include VLSI design with particular emphasis on energy-efficient resilient circuits and security based circuit design.

Tutorial 3

New Rules: Managing Processor Physics to Sustain Performance Scaling

Prof. Sudhakar Yalamanchili, Georgia Tech

Summary: As industry moves to increasingly small feature sizes, performance scaling will become increasingly dominated by the physics of the computing environment. There are fundamental trade-offs to be made at the microarchitectural level between performance, energy/power, and reliability. We refer to the body of knowledge addressing the impact of physics on such system level metrics as the processor physics. New efforts are emerging that are targeting understanding, characterizing, and collaboratively managing the multi-physics and multi-scale (nanoseconds to milliseconds) transient interactions between the delivery, dissipation, and removal (cooling) of energy and their impact on system level performance. In particular, these tradeoffs must be driven by application workloads. This talk will describe how interacting physical phenomena can affect application driven microarchitecture-level tradeoffs and lead to operational principles for energy-efficient multicore architectures. In particular, the talk will cover recent work on improved dynamic power management in a commodity heterogeneous processor.

About Prof. Sudhakar Yalamanchili
Sudhakar Yalamanchili earned his Ph.D degree in Electrical and Computer Engineering in 1984 from the University of Texas at Austin. Upon graduation, he joined Honeywell's Systems and Research Center in Minneapolis working on embedded multiprocessor architectures. He joined the ECE faculty at Georgia Tech in 1989 where he is now a Joseph M. Pettit Professor of Computer Engineering. He is the author of two texts on VHDL-based simulation modeling and synthesis, and co-author with J. Duato and L. Ni, of Interconnection Networks: An Engineering Approach, Morgan Kaufman, 2003. His current research foci lie in addressing the software challenges of heterogeneous architectures and solutions to power and thermal issues in many core architectures and systems. Since 2003 he has been a Co-Director of the NSF Industry University Cooperative Research Center on Experimental Computer Systems at Georgia Tech. Dr. Yalamanchili regularly contributes professionally on editorial boards and program committees in high performance computing and computer architecture

Tutorial 4

Very Large Scale Analog (VLSA): Synthesizing Cell-Based ADPLLs with Digital CAD Tools

Prof. David D. Wentzloff , University of Michigan

Summary: As CMOS processes scale and digital gates become faster, it is practical to implement precisely-timed digital circuits switching in the GHz range that are synthesized using standard cell libraries and digital IC design flows. In parallel, the number of design for manufacturability checks has grown at an exponential rate in recent scaled CMOS processes, making full-custom analog design of CMOS ICs more challenging and time-consuming. As a result, traditionally analog circuits, such as those for clock generation and analog/digital conversion, have moved towards mostly-digital designs, significantly leveraging accurate time control and digital signal processing. This tutorial will focus on design techniques for implementing cell-based, all-digital PLLs that are synthesized using digital CAD flows. Recent results will be presented from a 400MHz ADPLL designed for the WBAN standard, and a 150-500kHz programmable clock generator for ultra-low power processors.

About Prof. David D. Wentzloff
David D. Wentzloff received the B.S.E. degree in Electrical Engineering from the University of Michigan, Ann Arbor, in 1999, and the S.M. and Ph.D. degrees from the Massachusetts Institute of Technology, Cambridge, in 2002 and 2007, respectively. In the summer of 2004, he worked in the Portland Technology Development group at Intel in Hillsboro, OR. Since August, 2007 he has been with the University of Michigan, Ann Arbor, where he is currently an Associate Professor of Electrical Engineering and Computer Science. His research focuses on ultra-low power and cubic-mm wireless sensors, and VLSA – cell-based analog circuit design synthesized using digital CAD flows. He is the recipient of the 2009 DARPA Young Faculty Award, 2009-2010 Eta Kappa Nu Professor of the Year Award, 2011 DAC/ISSCC Student Design Contest Award, 2012 IEEE Subthreshold Microelectronics Conference Best Paper Award, and the 2012 NSF CAREER Award. He has served on the technical program committee for ICUWB 2008-2010, ISLPED 2011-2012 and RFIC 2013, and as a guest editor for the IEEE T-MTT, the IEEE Communications Magazine, and the Elsevier Journal of Signal Processing: Image Communication.

Tutorial 5

CMOS Biosensors for Molecular Diagnostics and Cellular Monitoring

Prof Hua Wang, Georgia Institute of Technology

Summary: Complementary Metal–Oxide–Semiconductor (CMOS), as one of the most matured integrated circuit (IC) processes, has gained increasing attention among the biosensors and bioelectronics community. Advanced CMOS process provides high-performance signal receiving and generation, unparalleled on-chip computation, and low cost at a mass-production level. As a result, CMOS ICs naturally offer a powerful, versatile, and cost-competitive platform for implementing integrated biosensors. In this talk, we will review several common sensor modalities which have been successfully implemented in CMOS process to address low-cost high-throughput molecular diagnostics and cellular monitoring applications. In particular, CMOS-based magnetic biosensors, as an emerging sensing modality, will be discussed. Several different CMOS-based magnetic sensing schemes will be covered, and their trade-offs among various sensor performance metrics will be compared.

About Prof Hua Wang
Hua Wang received his M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 2007 and 2009, respectively. He worked as an integrated circuit designer and project lead at Intel Corporation and Skyworks Solutions. He joined the School of Electrical and Computer Engineering at Georgia Institute of Technology as an assistant professor in 2012. He is interested in innovating mixed-signal, RF, and mm-Wave integrated systems for bioelectronics, medical instrumentation, and wireless communication. His research group, Georgia Tech Electronics and Micro-System Lab (GEMS), is currently developing CMOS-based low-cost bioelectronics and spectrometers, noise modeling in biosensors, reconfigurable RF circuits, and silicon-based THz electronics. Dr. Wang was the award receipt of the 46th IEEE DAC/ISSCC Student Design Contest Winner in 2009 and ISSCC Analog Devices Inc. Outstanding Student Designer Award in 2008. He is currently a Technical Program Committee (TPC) Member for IEEE RFIC, CICC, and BCTM conferences.

Tutorial 6

Emerging Materials for Energy Efficient Devices

Prof. Sayeef Salahuddin, University of California at Berkeley

Summary: Driven by the need of energy efficiency and scaling, research in electronic devices in the recent years has focused heavily on new materials and new phenomena, in part to go beyond the capabilities enabled by traditional Si CMOS technology. In this talk, I shall discuss three examples: (i) Two dimensional semiconductors, (ii) Ferroelectric materials and (ii) Magnetic materials. All these material systems are currently receiving significant effort from researchers all over the world. In each case, I shall describe our own perspectives as to their potential use for next generation electronics. I shall also discuss specific examples where these materials could lead to applications otherwise difficult to obtain by traditional means.

About Prof. Sayeef Salahuddin
Sayeef Salahuddin received his B.Sc. in Electrical and Electronic Engineering from BUET (Bangladesh University of Engineering and Technology) in 2003 and PhD in Electrical and Computer Engineering from Purdue University in 2007. He joined the faculty of Electrical Engineering and Computer Science at University of California, Berkeley in 2008. His research interests are in the interdisciplinary field of electronic transport in nano structures currently focusing on novel electronic and spintronic devices for low power logic and memory applications. Salahuddin has championed the concept of using 'interacting systems' for switching, showing fundamental advantage of such systems over the conventional devices in terms of power dissipation. He received the Kintarul Haque Gold Medal from BUET in 2003, the Meissner fellowship from Purdue University, 2003-4, an IBM PhD Fellowship 2007-8, a MARCO/FCRP Inventor Recognition Award in 2007, a UC Regents Junior Faculty Fellowship in 2009, a Hellman Faculty Fellowship in 2010, a DOE NISE award in 2010, the NSF CAREER award in 2011, the IEEE Nanotechnology Early Career Award in 2012, an AFOSR Young Investigator Award in 2013 and an ARO Young Investigator Award in 2013.