Elyse Rosenbaum

About Elyse Rosenbaum

Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She received the Ph.D. degree in electrical engineering from University of California, Berkeley. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a joint project of the University of Illinois, Georgia Tech and North Carolina State University. Her current research interests include component and system-level ESD reliability, ESD-robust high-speed I/O circuit design, compact modeling, circuit reliability simulation, mitigation strategies for ESD-induced soft failures, and machine-learning aided behavioral modeling of microelectronic components and systems. Dr. Rosenbaum has authored or co-authored nearly 200 technical papers; she has been an editor for IEEE Transactions on Device and Materials Reliability and IEEE Transactions on Electron Devices. She was the recipient of a Best Student Paper Award from the IEDM, Outstanding and Best Paper Awards from the EOS/ESD Symposium, a Technical Excellence Award from the SRC, an NSF CAREER award, an IBM Faculty Award, and the ESD Association’s Industry Pioneer Recognition Award. She is a Fellow of the IEEE.

Mark Ren

About Mark Ren

Haoxing (Mark) Ren is a principal research scientist at NVIDIA. His current research interests are machine learning application in design automation and GPU accelerated EDA. He worked at IBM EDA Lab from 2000 to 2006 where he was a key developer of placement tools. He joined IBM Research DA group in 2007 where he led the development of logic ECO synthesis tools and high-level synthesis tools. Prior to joining NVIDIA in May 2016, he was a technical executive at PowerCore, a startup developing server-class CPUs as part of the IBM OpenPower initiative. Mark holds over twenty patents and co-authored many papers including several book chapters in physical design and logic synthesis. He is an IEEE senior member and served as a TPC member for ICCAD and DAC. Mark earned a PhD degree in Computer Engineering from University of Texas at Austin, a M.S. degree in Computer Engineering from Rensselaer Polytechnic Institute, and a B.S. degree in Electrical Engineering from Shanghai Jiao Tong University.

Noel Menezes

About Noel Menezes

Noel Menezes is the director of Intel’s Strategic CAD Labs department which is part of Intel Labs’ Architecture and Design Research division. Noel leads a team of researchers exploring design methodologies and tools to accelerate Intel’s product development cycle in various areas of system- and silicon-level design and validation including firmware. He is a member of the Intel Corporate Research Council and is involved in driving academic research in related areas. He holds graduate degrees from the University of Texas at Austin.

Pradiptya Ghosh

About Pradiptya Ghosh

Pradiptya Ghosh is Sr. Director of Engineering responsible for Calibre Semi-manufacturing Products and has been with Mentor since 2007. During his time he launched 12 research programs that got converted into products like Double Patterning/Multi Patterning, Cluster Management, MB-SRAF, nmbias(retargeting tool), nmModelFlow, MPC and Calibre FullScale etc. He is currently actively involved in research initiatives in the domain of Computational Intelligence applicability to Design & Manufacturing, HPC and longer-range research programs. Besides core technical work, he was at point for acquisition of Softjin Litho group and also bringing in AWS infrastructure for Calibre product development. He represents Mentor on the Industry Board of SJSU-MESA(Vice-Chair) and CDEN(UC Berkeley/UCLA/UCSD research program in Process, Device, Design and CAD). Previous to Mentor, he led architecture evaluation team for 5 FPGA families at Lattice Semiconductor and worked on datapath design/CAD tools for 5 generation of Sun Microsystem’s UltraSparc (USparc2-USparc5 and Javachip). He has a MS in Computer & System Engg from Rensselaer Polytechnic Institute and Certification of Business Excellence from Haas School, UC Berkeley. He has a few paper and patents in place and route, multi-patterning, DFM(related to alt-PSM), Mask Data Preparation and Cluster resource management.

Sachin Sapatnekar

About Sachin Sapatnekar

Sachin Sapatnekar is a Distinguished McKnight University Professor and the Henle Chair Professor in Electrical and Computer Engineering at the University of Minnesota. He received the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1992. His current research focuses on CAD techniques for the analysis and optimization of digital and analog circuits in CMOS and emerging technologies. He has served as Editor-in-Chief of the IEEE Transactions on CAD and General Chair for the ACM/IEEE Design Automation Conference (DAC). He is a recipient of several conference Best Paper Awards, ten-year retrospective Best Paper Awards, the Semiconductor Research Corporation's Technical Excellence Award, and the Semiconductor Industry Association University Research Award. He is a Fellow of the IEEE and the ACM.

Manish Pandey

About Manish Pandey

Dr. Manish Pandey is a Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and B.S. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for Machine Learning and Systems, Formal Verification and Power Analysis at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. He also has extensive experience in distributed systems and computing infrastructure, when he led the display advertising security group at Yahoo, and storage analytics systems at Nutanix. Dr. Pandey has been the recipient of the IEEE Transaction in CAD Outstanding author award, and holds over two dozen patents and referred publications.