ISQED 2009 |
Small Embeddable NBTI Sensors (SENS) for Tracking On-Chip Performance Decay Adam Cabe, Zhenyu Qi, Stuart Wooters, Travis Blalock, Mircea Stan University of Virginia |
Power & Variability Test Chip Architecture and 45nm-Generation Silicon-Based Analysis for Robust, Power-Aware SoC Design Ramnath Venkatraman, Ruggero Castagnetti, Andres Teene, Benjamin Mbouombouo, Shiva Ramesh LSI Corporation |
3D-GCP: An Analytical Model for the Impact of Process Variations on the Critical Path Delay Distribution of 3D ICs Siddharth Garg and Diana Marculescu Carnegie Mellon University |
ISQED 2008 |
A methodology for characterization of large macro cells and IP blocks considering process variations |
Characterization of Standard Cells for
Intra-Cell Mismatch Variations |
Design Margin Exploration of Spin-Torque
Transfer RAM (SPRAM) |
ISQED 2007 |
Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications Amit Laknaur, Rui Xiao, Sai Raghuram Durbha, Haibo Wang Southern Illinois University, Carbondale |
Arthur Nieuwoudt and Yehia Massoud Rice University |
A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances Andrew B. Kahng and Rasit O. Topaloglu University of California San Diego |
ISQED 2006 |
Improving Transient Error Tolerance of Digital VLSI
Circuits Using
Robustness Compiler (ROCO)
Chong Zhao, Sujit Dey
|
System-Level SRAM Yield Enhancement
Fadi Kurdahi *, Ahmed Eltawil
*, Rouwaida Kanj **,
*UC Irvine,
|
Power Gating with Multiple Sleep Modes
Kanak Agarwal*, Harmander
Deogun**, Dennis Sylvester**, Kevin Nowka*
*IBM Research,
|
FASER: Fast Analysis of Soft Error Susceptibility for
Cell-Based Designs
Bin Zhang, Wei-shen
Wang, Michael Orshansky
|
ISQED 2005 |
Noise Library Characterization for Large Capacity Static Noise Analysis Tools Alex Gyure, Alireza Kasnavi, Sam Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zedja Synopsys Inc., Mountain View, CA |
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin IBM Corp., Yorktown Heights, NY |
A New Method for Robust Design of Digital Circuits Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen Boyd Stanford University, Stanford, CA |
A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing Xin Wang, Charles Chiang, Jamil Kawa, Qing Su Synopsys Inc., Mountain View, CA |
ISQED 2004 |
SRAM
Leakage Suppression by Minimizing Standby Supply Voltage |
Scan BIST Targeting Transition Faults Using a Markov
Source |
Application Specific Worst Case Corners using Response
Surfaces and Statistical Models |
Robustness Enhancement through Chip-Package Co-Design for
High-Speed Electronics |
ISQED 2003 |
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay Takashi Sato*, Hiroo Masuda** *Hitachi, Ltd., Kyoto University,Tokyo, Japan, **Semiconductor Technology Academic Research Center, Kanagawa, Japan |
ISQED 2002 |
Pre-route Noise Estimation in Deep Submicron Integrated Circuits Murat R. Becer*, Rajendran Panda*, David Blaauw**, Ibrahim N. Hajj*** *Motorola, **University of Michigan, ***American University, Beirut |
ISQED 2001 |
Color Counting and its Application to Path Delay Fault Coverage Jayant Deodhar*, Spyros Tragoudas** *Intel, **Southern Illinois University |
A System for Automatic Recording and Prediction of Design Quality Metrics Andrew B. Khang, Stefanus Mantik UCLA |
ISQED 2000 |
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques Zhanping Chen*, Liqiong Wei*,Kaushik Roy** *Intel, Purdue University |
Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells Tomas Bautista and Antonio Nunez University of Las Palmas de Gran Canaria |
Quick On-Chip Self- and Mutual-Inductance Screen Shen Lin, Norman Chang, Sam Nakagawa Hewlett-Packard Laboratories |