ISQED'26 Embedded Tutorials
Chair & Moderators:
Na Gong - University of Alabama(Chair)
Tutorial 1
Wednesday, April 8, 12:25PM-1:25PM
Advanced Packaging: Current State and Looking Forward
Presenter:
Dr. William Lambert, AMD
William LambertAbstract: Advanced packaging is now an essential component of high-performance SOC design, spanning applications from low-cost consumer CPUs to leading-edge AI processors. For AI applications in particular, advanced packaging is indispensable – it is the only way to enable the integration of large compute area, high memory capacity, and massive memory bandwidth required for competitive products. This tutorial will provide an overview of advanced packaging strategies currently in use, including hybrid bond stacking, silicon interposer, and fan-out bridge technologies, with a focus on their implementation in AMD products. Next, future directions for scaling these technologies will be reviewed with an emphasis on how new concepts in SOC architecture and circuit design may drive “Design Technology Co-Optimization” (DTCO) in years to come. Finally, the tutorial will review how adjacent areas are developing to support the disaggregated designs enabled by advanced packaging, including package and silicon design and verification tools, electrical and mechanical simulation tools, sort, and test.
About
William Lambert
William Lambert is a Fellow of AMD, Inc. where he leads a team creating the packaging solutions for next-generation AI products. He previously worked on packaging solutions for datacenter and client GPUs and CPUs. Prior to joining AMD, he was a Senior Principal Engineer in the Assembly & Test Technology Development group at Intel Corporation, where he held leadership roles in packaging architecture definition, power delivery and integrated voltage regulation technology development, and RF packaging development. He received his Ph.D. in electrical engineering from Arizona State University with a focus on low-voltage DC-DC power electronics for computer systems, and his M.S. and B.S. degrees from Rochester Institute of Technology.
Tutorial 2
Thuesday, April 9, 1:05PM-2:05PM
Efficient In-Memory Computing AI Chip Hardware-Software Co-Design
Presenter:
Prof. Deliang Fan , Arizona State University, Tempe, AZ
Deliang FanAbstract: In-memory computing is becoming a promising solution to overcome the well-known ‘memory-wall’ challenge, through directly processing the data within memory where data is stored. Therefore, it will reduce massive power hungry data traffic between computing and memory units, leading to significant improvement of entire system performance and energy efficiency. Many different memory technologies have been explored for the design of compute-in-memory (CIM) or in-memory computing (IMC), such as emerging post-CMOS Magnetic Random Access Memory (MRAM), Resistive RAM (ReRAM), or silicon based Static Random Access Memory (SRAM) and Dynamic RAM (DRAM), etc. In this talk, Prof. Deliang Fan, from Arizona State University (ASU), will present state-of-the-art research in energy efficient and intelligent cross-layer in-memory computing AI chip design spanning from new memory technologies, compute-in-memory circuit & chip design demos, and hardware-aware AI model optimization.
About Deliang Fan
Dr. Deliang Fan is currently an Associate Professor in the School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA. He received his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Purdue University, West Lafayette, IN, USA, in 2012 and 2015, respectively. Dr. Fan’s primary research interests include AI Hardware, Digital Chip Design, Efficient AI algorithm, In-Memory Computing Circuits and Architecture, Adversarial and Trustworthy AI System. Dr. Fan is the co-founder of an AI chip startup. Dr. Fan has authored around 190 peer-reviewed international journal/conference research papers. He is the receipt of National Science Foundation Career Award, best paper award of 2019 ACM Great Lakes Symposium on VLSI, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), and 2017 IEEE ISVLSI, best IP paper award of 2022 Design Automation and Test in Europe (DATE). His research works were also nominated as best paper candidate 2021 Design Automation Conference (DAC), 2019 Asia and South Pacific Design Automation Conference (ASPDAC) and 2019 International Symposium on Quality Electronic Design (ISQED). He is also the TPC Chair/Co-Chair of ISQED 2023-2026, chair of iMACAW@DAC 2022-2025, technical area chair of DAC 2021/2025, GLSVLSI 2019-2022, ISQED 2019-2022. He served as technical reviewers for 30+ international journals/conferences, such as Nature Electronics, IEEE TNNLS, TVLSI, TCAD, TNANO, TC, TCAS, etc. He also served as the Technical Program Committee member of DAC, ICCAD, HPCA, MICRO, AAAI, WACV, GLSVLSI, ISVLSI, ASP-DAC, etc. Dr. Fan served as the guest editor of IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Journal on Emerging and Selected Topics in Circuits and Systems, IEEE Transactions on Emerging Topics in Computing (TETC), Frontiers in Physics, etc. Dr. Fan is a senior member of IEEE and ACM. Please refer to his research website for more details: https://faculty.engineering.asu.edu/dfan/