ISQED Summit 2018)

ISQED SUMMIT 2018 Speakers

Tuesday & Wednesday March 13-14

Challenges and Opportunities of High Bandwidth Memory

Kevin Widmer Kevin Widmer

Kevin Widmer - VP Technical Marketing - SK Hynix America

TBA

 

 

 

 

About Kevin Widmer

Kevin Widmer is VP of Technical Marketing at SK hynix America Inc., a leading manufacturer of DRAM, NAND and SSD products. Prior to joining SK hynix in 2013, Mr. Widmer served in various product definition, product planning and strategic marketing roles at Micron Technology and Spansion (now Cypress Semiconductor). Mr. Widmer holds BS Physics, BSEE, and MBA degrees from Florida Atlantic University and has been awarded 20 USPTO patents related to semiconductor memory technology.

New Packaging Alternatives via high bandwidth and low power USR SerDes

Amin Shokrollahi Amin Shokrollahi

Amin Shokrollahi Ph.D. - CEO - Kandou Bus

Massive integration of IC components on a chip has been the primary catalyst for the development of high performance Systems on Chip (SoC). Today, SoC’s contain a multitude of components besides the logic core that makes up the main functionality. Integration of these components is fast becoming the major bottleneck in the design and development of SoC’s. Verification alone can take up to 70% of the design time, especially when high speed analog components have to be integrated alongside digital ones. The tide is therefore changing in the industry, with disintegration gaining more traction. “Chiplets”, or stand alone die with defined functions in heterogenous processes, can be packaged together to create a disintegrated SoC. To allow maximum flexibility in terms of die placement and heterogeneity, as well as lowest packaging costs, ultra-short-reach (USR) SerDes can be used to connect chiplets in a standard MCM. For such SerDes to be competitive, it needs to have extremely high bandwidth, and be of lowest possible power. In this talk I will introduce such a SerDes family, called “Glasswing,” discuss some of the theory behind its development, and outline today’s and future applications.

About Amin Shokrollahi

Amin Shokrollahi received his PhD at the University of Bonn in 1991. He is a full professor at EPFL in Lausanne and the CEO of Kandou Bus, a company he founded in 2011. He has more than 150 publications in different areas, and more than 120 pending and granted patent applications. An IEEE Fellow, his honors include the IEEE Eric Sumner Award (2007), the IEEE Hamming Medal (2012), the ISSCC best paper Award (2014), and the $500,000 Mustafa Award for ICT (2017).

TBA

Santosh Kumar

Santosh Kumar - Senior Technology and Market Analyst - Yole Développement

TBA

 

 

 

About Santosh Kumar

Santosh Kumar is currently working as Senior Technology & Market Research Analyst at Yole Développement. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging. He received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.

The art of managing, planning and optimizing 2.5D heterogeneous systems

Taylor Hogan Taylor Hogan

Taylor Hogan - Technology Architect for SPB Division - Cadence Design Systems

TBA

 

 

 

About Taylor Hogan

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HBM2 versus DDR4 - Implications for Your SoC Design When Integrating HBM2 Interfaces

Graham Allan Graham Allan

Graham Allan - Sr. Staff, Product Marketing Manager, Synopsys

TBA.

 

 

About Graham Allan

Graham Allan joined Synopsys in June 2007. Prior to joining Synopsys, Mr. Allan was with MOSAID Technologies as Director of Marketing for Semiconductor IP. With over 30 years of experience in the memory industry, Mr. Allan has spoken at numerous industry conferences. A significant contributor to the SDRAM, DDR and DDR2 JEDEC memory standards, Mr. Allan currently holds 25 issued patents in the area of memory design.

Enabling programmable customization in SiP devices

Alireza Kaviani Alireza Kaviani

Alireza Kaviani - Office of CTO, Xilinx

Complexity of building monolithic semiconductor devices is rapidly increasing, stretching design cycles to several years for the latest technology nodes. At the same time, System in Package (SiP) solutions are emerging that mitigate this complexity increase. Beyond mitigation, however, the SiP era along with customization power of programmable devices may unlock an opportunity. Will this lead to a new design paradigm for edge computing devices? FPGAs are programmable platforms that provide domain customization for medium to low volume systems. Xilinx pioneered 2.5D interposer-based devices in 2011 and has recently announced 16nm HBM devices as part of the 3rd generation of 3D FPGAs. In this talk, we review these latest SiP devices that boast more than 8GB memory, delivering 20X higher bandwidth than that of DDR SDRAM. Dynamics and challenges of using these devices are discussed in the context of data-intensive applications such as machine learning and hardware acceleration for cloud servers. Looking forward, we explore how customization benefits of FPGAs can be highlighted with various SiP scenarios in terms of cost and power. Finally, we provide insights on relevant emerging trends as applications expand from cloud servers to the intelligent computing devices at the edge of the cloud.

About Alireza Kaviani

Alireza Kaviani is a distinguished Engineer at Xilinx Research Labs with a focus on the next generation FPGA architectures and tools. He has more than 20 years of FPGA and ASIC industry experience in the areas of architecture, tools, IC design, and applications. Alireza has authored more than 50 patents and publications in a number of areas, including clocking, asynchronous design, FPGA architecture and CAD tools. He holds a PhD degree from University of Toronto in Electrical and Computer Engineering.

AI Creating New Opportunities for Chip Designers

Yankin Tanurhan Yankin Tanurhan

Yankin Tanurhan - Vice President Engineering, Synopsys

Rapid advances in artificial intelligence (AI) and machine learning are creating the next wave of opportunities for SoC designers. From facial recognition to surveillance monitoring to autonomous driving, AI is becoming must-have technology for an expanding number of tech applications. Neural networks, modeled after the human brain, have significantly improved developers’ ability to implement machine learning hardware and software in edge devices, particularly for object detection and embedded vision applications. This keynote presentation provides an industry perspective on AI trends and emerging uses.

About Yankin Tanurhan

Dr. Yankin Tanurhan is Vice President Engineering, DesignWare Processor Cores, IP Subsystems, Non-Volatile Memory at Synopsys leading low power and high-performance ARC and EV Embedded Processor developments targeted from Mobile, IoT, Embedded Vision, AI/ML, Digital Home, Automotive/Industrial, Security to Storage markets. His portfolio additionally includes ASIP tool development with products like ASIP Designer and Programmer, IP Subsystems products like Sensor Fusion, Audio, Vision and Security Subsystems and CMOS based Non-Volatile Memory IP development. Dr. Tanurhan has authored 100+ papers in refereed publications. He holds a B.S. and M.S. in Electrical and Computer Engineering from Rheinisch Westfaellische Technische Hochschule (RWTH) in Aachen, Germany and a Dr. Ing. degree summa cum laude in Electrical Engineering from the University of Karlsruhe (TH) in Karlsruhe, Germany.

Computer vision tools to further understanding the development of infant’s visual focus of attention

Qazaleh Mirsharif Qazaleh Mirsharif

Qazaleh Mirsharif - Machine Learning Scientists, CrowdFlower

Head cameras allow scientists to obtain vast quantities of video data from the momentary visual experiences of camera wearers, providing a unique perspective of the world that is human-centric. Scientists mount these cameras on infants to access their visual field and study infant’s visual attention and its role in his/her development. They setup experiments where infant and one parent are engaged in a tabletop toy play and collect their visual field using head cameras. They analyze the egocentric videos and infant’s behavior frame by frame to understand how infants visually approach objects and assign names to those objects which is a time-consuming process and requires high-level of expertise. Computer vision has been emerging in this field recently for developing faster and more accurate tools for quantitative analysis of such videos. In this presentation, we show how use of computer vision tools can help scientists discover patterns in the development of visual attention in infants which cannot be estimated by human analysis as the head camera is in constant motion.

About Qazaleh Mirsharif

Qazaleh Mirsharif is a Machine Learning Scientists specializing in Computer Vision. She has received a PhD in computer science from University of Houston, Texas focusing on applications of computer vision in developmental studies of children. She received her MSc in Artificial intelligence and has worked on areas as diverse as medical image processing, object segmentation and motion analysis in videos and parking sign detection in street view images.

Artificial Intelligence In Autonomous Vehicles

Gaurav Agarwal Gaurav Agarwal

Gaurav Agarwal - Automotive Marketing - NVIDIA

Building a self-driving technology which can understand the nuances of the world and drive in all the scenarios is a hard problem. Driving in bad weather conditions e.g. snow when there is no lane markings, complex urban streets, construction zones etc are some examples. Artificial intelligence can help solve some of these issues. In this talk, the latest trends and challenges in Autonomous driving will be presented. Then the talk with discuss the role of Artificial intelligence/deep learning to enable this technology.

About Gaurav Agarwal

Gaurav currently supports Business Development for Automotive at NVIDIA. Before this role, he was responsible for product management for NVIDIA Autonomous Driving SDK “DriveWorks”. Previously he has held business development, marketing and engineering leadership roles at Texas Instruments. Gaurav did his B.S. and M.S. in Electrical engineering and has several publications in the area of image processing and computer vision and holds two US patents.

Heterogeneous Chip Architectures for Big Data Machine Learning Analytics

Houman Homayoun Houman Homayoun

Houman Homayoun, Ph.D. - CTO - Green Silica

Emerging data analytics applications rely heavily on deep machine learning and mining algorithms, and are running complex database software stack with significant interaction with I/O and OS and sharing many inherent characteristics that are fundamentally different from traditional CPU applications. Emerging big data applications require computing resources that can efficiently scale to manage massive amounts of diverse data. However, the rapid growth in the data, as well as physical design constraints, such as power and density, yields challenges to process them efficiently using current homogeneous cloud server architectures. To respond to these challenges, heterogeneous architectures which integrates big and little cores with FPGA accelerators has emerged as a promising solution. In this talk, through methodical investigation of power and performance measurements, we first show the characterization results of emerging big data applications on big Xeon and little Atom-based servers to show whether heterogeneous architectures are needed for efficient processing. Second, we will show how in a heterogeneous architecture effective mapping of big data applications to FPGA accelerator can significantly increase the energy-efficiency and performance.

About Houman Homayoun

Houman Homayoun is an Assistant Professor of the Department of Electrical and Computer Engineering at George Mason University (GMU). Prior to joining GMU, Houman spent two years at the UC- San Diego, as National Science Foundation Computing Innovation (CI) Fellow awarded by the Computing Research Association (CRA) and the Computing Community Consortium (CCC). Houman’s research is in big data computing, heterogeneous computing, and hardware security and trust. He is currently leading several research funded projects (a total of $7.2 million), supported by DARPA, NSF, NIST, GM, and AFRL on heterogeneous computing and hardware security. He received the 2016 GLSVLSI conference best paper award. He is currently serving as an Associate Editor of IEEE Transactions on VLSI (TVLSI). Houman is the co-founder of Green Silica.

Memory-Centric Architectures for Artificial Intelligence

Paul Franzon Paul Franzon

Paul Franzon - Professor - North Carolina State University

There is much current interest in building custom accelerators for machine learning and machine intelligence algorithms. However, at their root, many of these algorithms are very memory intensive in both capacity and bandwidth needs. Thus there is a need for memory-processor codesign to obtain the most of these algorithms. This talk presents multiple options to achieve high performance. A 3DIC logic on memory stack has been designed to support the compute needs for multiple parallel inference engines running deep networks simultaneously, for example as would be needed for autonomous vehicles. The DRAM is adopted from the Tezzaron DiRAM4 but supports over 130 Tbps of memory bandwidth with potential for 64 GB of capacity. A Processor In Memory architecture with Application Specific Instruction features has been designed to support Sparse Hierarchical Temporal algorithms that permit in-situ learning. These achieve an improvement in performance over a GPU implementation of over 20x and a power efficiency improvement of over 500x. Currently we are designing 2.5D versions of these accelerators as well as accelerators for quantized deep learning and Long Short Term Memory (LSTM) algorithms. Preliminary results from this activity will be presented.

About Paul Franzon

Paul D. Franzon is currently the Cirrus Logic Distinguished Professor of Electrical and Computer Engineering and Director of Graduate Programs for ECE at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he cofounded, Communica, LightSpin Technologies and Polymer Braille Inc. His current interests center on the technology and design of complex microsystems incorporating VLSI, advanced packaging and nano-electronics. He has lead several major efforts and published over 300 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, and received the Alcoa Research Award in 2005. He served with the Australian Army Reserve for 13 years as an Infantry Solider and Officer. He is a Fellow of the IEEE.


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