International Symposium on Quality Electronic Design (ISQED)

ISQED 2013 Conference At-a-Glance

Monday, March 4, 2013


ISQED 2013 Tutorials

Best Design Practices for Modern Integrated Circuits

Room: Fremont


IC Technology at New Nodes Made Easy, Dr. Alvin Loke - AMD

Physical Design Considerations for Silicon Nanophotonic Circuits, Dr. Ron Ho - Oracle

Design of 3D ICs: From Concept to Practice, Prof. Sung Kyu Lim - Georgia Tech

Computer Architecture Design Utilizing Novel Memories, Prof. Engin Ipek - University of Rochester

Hardware Security and Implications on Design Flows, Prof. Ozgur Sinanoglu - NYU Abu Dhabi

Holistic Power Managemen, Vinod Viswanath - Realintent, Rajeev D. Muralidhar - Intel, & Hari Seshadri - Intel

Tuesday, March 5, 2013


Plenary Session 1P

Room: Silicon Valley


Moderated by:

Dr. Chi-Foon Chan

President and Co-CEO, Synopsys

Keynote Speeches:

The Changing Device Technology

Chenming Hu - TSMC Distinguished Professor of Graduate School, University of California, Berkeley

Sustaining Innovation for Smarter Computing in Data Centers

Brad L Brech - Member of the IBM Academy of Technology, IBM

System Level Perspective on Semiconductors for Intelligent Networks

Bill Swift - Vice President of Engineering Cisco Systems


Morning Break



10:20am–12 Noon

Session 1A

3D Circuits and Packaging

Room: San Jose

Session 1B

Aging aware design


Room: New Almaden

Session 1C

3D Integrated Circuits


Room: Morgan Hill



12 Noon–1:30am

ISQED Luncheon

Room: Silicon Valley

ISQED Quality Award (IQ Award 2013)

ISQED Quality Quest Award (Q2 Award 2013)

Best Paper Awards

Committee Recognition Awards


Luncheon Speech

Trends in Analog/ Mixed-Signal Design Tools

Ed Petrus, Director of Custom Architecture, DSM division, Mentor Graphics



Session 2A

System Level Design/Optimization for Energy

Room: San Jose

Session 2B

Low Power System Design


Room: New Almaden

Session 2C

Emerging Devices and Design Techniques



Room: Morgan Hill




Afternoon Break


Session 3A

Advances in Routing and Timing

Room: San Jose

Session 3B

Robust Design for Fault Tolerance

Room: New Almaden

Session 3C

CAD for 3-D ICs


Room: Morgan Hill




Poster Papers & Mixer

Room: Atrium


Wednesday, March 6, 2013


Plenary Session 2P

Room: Silicon Valley

Keynote Speeches

Physical-Aware, High-Capacity RTL Synthesis for Advanced Nanometer Designs

Sanjiv Taneja, Vice President, Product Engineering, Front End Design - Cadence Design Systems


The Lifecycle Of Audio Products, consumer versus professional

Perry Goldstein , Director of Sales & Marketing - Marshall Electronics



Morning Break

10:20am–12 Noon

Session 4A

Low Power Technologies


Room: San Jose

Session 4B

Silicon Diagnosis and Test


Room: New Almaden

Session 4C

New Ideas in CAD


Room: Morgan Hill

12 Noon–1:30pm

Lunch Break


Session 5A

System Design Methodologies and Automation

Room: San Jose

Session 5B

Manufacturing and Modeling Issues of Nanoscale CMOS

Room: New Almaden

Session 5C

Multi-core and Multi-processor Systems


Room: Morgan Hill


Afternoon Break


Session 6A

Issues and Challenges in Characterization and Power Integrity for Nanometer Technologies

Room: San Jose

Session 6B

Low Power Circuits



Room: New Almaden

Session 6C

Reliable System Design



Room: Morgan Hill


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