ISQED 2024: Program (rev 0)

Wednesday April 3
                         Session 1A - Novel Integrated Circuits and Systems
Chair: Suyash Ranjan (suyash.ranjan@gmail.com), Qualcomm, San Diego
Co-Chair: tbd, tbd
10:20    Session 1A - 1A.1: HISPE: High-Speed Configurable Floating-Point Multi-Precision Processing Element
Tejas N1, Rakshit Bhatia1, Madhav Rao2
1IIIT-Bangalore, 2International Institute of Information Technology-Bangalore
10:40    Session 1A - 1A.2: A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS.
Prema Kumar Govindaswamy1, Mursina Khatun2, Vijay Shankar Pasupureddi1
1Indian Institute of Technology Bhubaneswar, 2a23ec09005@iitbbs.ac.in
11:00    Session 1A - 1A.3: A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Techonology
Srinivasa Rao Maram1, Boyapati Subrahmanyam2, Vijay Shankar Pasupureddi3
1IIT BBS, 2FH-Kaernten, 3Indian Institute of Technology Bhubaneswar
11:20    Session 1A - 1A.4: HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With An Offset-Compensated Comparator
Abdullah Sahruri1, Martin Margala1, Ugur Cilingiroglu2
1University of Louisiana at Lafayette, 2Yeditepe University
Wednesday April 3
                         Session 1B - TBD
Chair: Chidhambaranathan R, Synopsys Inc.
Co-Chair: tbd, tbd
10:20    Session 1B - 1B.1: Quantum Circuit Simulation with Fast Tensor Decision Diagram
Qirui Zhang, Mehdi Saligane, Hun Seok Kim, David Blaauw, Georgios Tzimpragos, Dennis Sylvester
University of Michigan
10:40    Session 1B - 1B.2: Dual Use Circuitry for Early Failure Warning and Test
Alexander Coyle1, Hui Jiang1, Jennifer Dworak1, Theodore Manikas1, Kundan Nepal2
1Southern Methodist University, 2University of St Thomas
11:00    Session 1B - 1B.3: RTL Simulation Acceleration with Machine Learning Models
Chandan Karfa1, Surajit Das2, Hetang Patel3, Disha Puri4, Anshul Jain4, Kartheek Bellamkonda3, Rahul Reddy3, Arijit Sur3, Pradip Prajapati5
1Indian Institute of Technology Guwahati, 2Postdoctoral Research Associate, 3IIT Guwahati, 4Intel, 5Inrtel
11:20    Session 1B - 1B.4: Automated Assertion Checker Generator and Information Flow Tracking for Security Verification
Miguel Alfaro Zapata and Zeljko Zilic
McGill University
Wednesday April 3
                         Session 1C - Quantum Computing
Wednesday April 3
                         Session 2A - Upstream Synthesis and Machine Learning
Chair: tbd, tbd
Co-Chair: tbd, tbd
13:30    Session 2A - 2A.1: Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs
Daniela Sanchez Lopera1, Robert Kunzelmann1, Endri Kaja2, Wolfgang Ecker1
1Technical University of Munich & Infineon Technologies AG, 2Technische Universität Kaiserslautern & Infineon Technologies AG
13:50    Session 2A - 2A.2: High-Level Synthesis for Microfluidic Biochips Considering Actual Volume Management and Channel Storage
Zhengyang Chen1, Yuhan Zhu1, Zhen Chen1, Zhisheng Chen2, Genggeng Liu1
1College of Computer and Data Science, Fuzhou University, 2School of Informatics, Xiamen University
14:10    Session 2A - 2A.3: Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
Mahdi Taheri1, Natalia cherezova2, Mohammad Saeed Ansari3, Maksim Jenihhin2, ALI Mahani4, Masoud Daneshtalab5, Jaan Raik2
1PhD researcher at Tallinn university of Technology, 2Tallinn University of Technology, 3University of Alberta, 4Shahid Bahonar University of Kerman, 5KTH Royal Institute of Technology
14:30    Session 2A - 2A.4: Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling
Zhengfeng Wu and Ioannis Savidis
Drexel University
14:50    Session 2A - 2A.5: SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits
Shan Shen, Zhiqiang Liu, Wenjian Yu
Tsinghua University
Wednesday April 3
                         Session 2B - Hardware Trojan Attacks and Detection
Chair: tbd, tbd
Co-Chair: tbd, tbd
13:30    Session 2B - 2B.1: A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans
Xingyu Meng1, Abhrajit Sengupta2, Kanad Basu1
1University of Texas at Dallas, 2New York University
13:50    Session 2B - 2B.2: Trojan Assets and Attack Vectors in Processors
Czea Sie Chuah1, Alexander Hepp2, Christian Appold1, Tim Leinmüller1
1DENSO Automotive Deutschland GmbH, 2Technical University of Munich, TUM School of Computation, Information and Technology
14:10    Session 2B - 2B.3: Trojan Attacks on Variational Quantum Circuits and Countermeasures
Subrata Das and Swaroop Ghosh
The Pennsylvania State University
14:30    Session 2B - 2B.4: FAST-GO: Fast, Accurate, and Scalable Hardware Trojan Detection using Graph Convolutional Networks
Mona Hashemi1, Ali Imangholi2, Amirabbas Momeni2, Siamak Mohammadi3, Trevor E. Carlson4
1School of ECE, College of Eng., University of Tehran, and School of Computing, National University of Singapore, 2School of ECE, College of Eng., University of Tehran, 3School of ECE, College of Eng., University of Tehran, and School of Computing Science, IPM, 4National University of Singapore
Wednesday April 3
                         Session 2C - DNN Acceleration
Chair: tbd, tbd
Co-Chair: tbd, tbd
13:30    Session 2C - 2C.1: Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms
Steven Colleman1, Arne Symons1, Victor Jung2, Marian Verhelst1
1KULeuven, 2ETH Zurich
13:50    Session 2C - 2C.2: Roofline Performance Analysis of DNN Architectures on CPU and GPU Systems
Prashanth H C1 and Madhav Rao2
1IIIT-Bangalore, 2International Institute of Information Technology-Bangalore
14:10    Session 2C - 2C.3: PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN
Dantu Nandini Devi1, Gandi Ajay Kumar2, Bindu G Gowda2, Madhav Rao3
1International Institute of Information Technology Bangalore, 2international institute of information technology, bangalore, 3International Institute of Information Technology-Bangalore
14:30    Session 2C - 2C.4: DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization
Behnam Ghavami1, Amin Kamjoo1, Lesley Shannon1, Steve Wilton2
1Simon Fraser University, 2UBC
Thursday April 4
                         Session PW1 - Poster & WIP Session 1
Chair: tbd, tbd
Co-Chair: tbd, tbd
9:40    Session PW1 - PW1.1: Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives
Soramichi Akiyama1, Ryota Shioya2, Yuto Miyatake3, Tongxin Yang4
1Ritsumeikan University, 2The University of Tokyo, 3Osaka University, 4Sony Semiconductor Solutions Corporation
9:45    Session PW1 - PW1.2: An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods
Endri Kaja1, Nicolas Gerlin1, Bihan Zhao1, Daniela Lopera1, Jad Halabi1, Azam Khan1, Sebastian Prebeck1, Dominik Stoffel2, Wolfgang Kunz2, Wolfgang Ecker1
1Infineon Technologies AG, 2Rheinland-Pfalzische Technische Universität Kaiserslautern-Landau
9:50    Session PW1 - PW1.3: Timing-Driven High-Level Synthesis for Continuous-Flow Microfluidic Biochips
ZhengYang Ye1, Zhisheng Chen2, Youlin Pan3, Genggeng Liu3, Wenzhong Guo3, Tsung-Yi Ho4, Xing Huang5
1Fuzhou University, 2Xiamen University， Xiamen, 3Fuzhou University, Fuzhou, 4National Tsing Hua University, 5School of Computer Science, Northwestern Polytechnical University, Xi'an
9:55    Session PW1 - PW1.4: Swarm - A VLSI Timing, Fanout-aware Clustering Algorithm
Christos Sotiriou1, George Goudroumanis1, Nikolaos Sketopoulos1, Christos Georgakidis2
1Univesity of Thessaly - Department of Electrical and Computer Engineering (EECE), 2University of Thessaly
10:00    Session PW1 - PW1.5: FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization
Akash Levy1, Joe Walston2, Sourav Samanta2, Priyanka Raina1, Stelios Diamantidis2
1Stanford University, 2Synopsys, Inc.
10:05    Session PW1 - PW1.6: MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer Assignment
Zhenyi Gao, Sheqin Dong, Zifei Cheng, Wenjian Yu
Tsinghua University
10:10    Session PW1 - PW1.7: Graph Representation Learning Framework for Digital Integrated Circuit Design Automation
Pratik Shrestha and Ioannis Savidis
Drexel University
10:15    Session PW1 - PW1.8: Graph Neural Network-Based Detailed Placement Optimization Framework
DhoUI Lim1 and Heechun Park2
1Kookmin University, School of Electrical Engineering, 2Kookmon University
10:20    Session PW1 - PW1.9: Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
ROHIT GUPTA, Chiranjeev Grover, Etienne Maurin, Olivier Minez, Jean-arnaud Francois, Sebastien Marchal
STMicroelectronics
10:25    Session PW1 - PW1.10: Composite Sub-surface Model for RF GaN-HEMTs
Xing Zhou1, Wanlan Yang1, Siau Ben Chiah2
1Nanyang Technological University, 2New Silicon Corporation Pte Ltd
File
Thursday April 4
                         Session PW2 - Poster & WIP Session 2
Chair: tbd, tbd
Co-Chair: tbd, tbd
9:40    Session PW2 - PW2.1: Unleashing Energy-Efficiency: Neural Architecture Search without Training for Spiking Neural Networks on Loihi Chip
Shiya Liu and Yang Yi
Virginia Tech
9:45    Session PW2 - PW2.2: Advancing Analog Reservoir Computing through Temporal Attention and MLP Integration
Khalil Sedki and Yang Yi
Virginia Tech
9:50    Session PW2 - PW2.3: RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware
Shamik Kundu1, ARNAB RAHA2, Deepak Mathaikutty2, Kanad Basu1
1University of Texas at Dallas, 2Intel Corporation
9:55    Session PW2 - PW2.4: Exploring Model Poisoning Attack to Convolutional Neural Network Based Brain Tumor Detection Systems
Kusum Lata1, Prashant Singh2, Sandeep Saini2
1LNMIIT Jaipur, 2The LNM Institute of Information Technology, Jaipur
10:00    Session PW2 - PW2.5: Sensitivity Analysis of SOT-MTJs to Manufacturing Process Variation: A Hardware Security Perspective
Mousam Hossain1, Muhtasim Alam Chowdhury2, Ronald DeMara1, Soheil Salehi3
1University of Central Florida, 2University of Arizona, 3Department of Electrical and Computer Engineering, University of Arizona
10:05    Session PW2 - PW2.6: Lightweight Multicast Authentication in NoC-based SoCs
Hansika Weersena and Prabhat Mishra
University of Florida
10:15    Session PW2 - PW2.7: Trimming The Fat: A Minimum Security Architecture for Protecting SoC Designs Against Supply Chain Threats
Kshitij Raj1, Aritra Bhattacharyay2, Swarup Bhunia3, Sandip Ray4
1University of Florida, 2Department of Electrical and Computer Engineering, University of Florida, 3Department of Electrical and Computer Engineering, University of Florida, 4Department of Electrical and Computer Engineering, University of Florida, Gainesville
10:20    Session PW2 - PW2.8: ACT: Attributed Circuit Transformation System For Synthetic Circuit Generation
Juneeth kumar Meka and Ranga Vemuri
University of Cincinnati
10:25    Session PW2 - PW2.9: Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography
Capucine Berger-Sigrist1 and Andrea Guerrieri2
1EPFL, 2EPFL and HES-SO
File
10:30    Session PW2 - PW2.10: A Low-cost keyword spotting architecture based on wavelet packets feature extraction for edge devices
Sayed Salehi and Prakash Dhungana
University of Kentucky
File
Thursday April 4
                         Session PW3 - Poster & WIP Session 3
Chair: tbd, tbd
Co-Chair: tbd, tbd
9:40    Session PW3 - PW3.1: SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement Learning
Siqin Liu and Avinash Karanth
Ohio University
9:45    Session PW3 - PW3.2: SpotLight: A Hotspot-Greedy, Light-Weighted, and Automated Thermal Modeling Framework for Early Smartphone Design
Chin-Wei Wu1, Yu-Min Lee1, Pei-Yu Huang1, Bo-Jiun Yang2, Tai-Yu Chen2, Ting-Chang Huang2, Yen-Lin Lee2
1National Yang Ming Chiao Tung University, 2Mediatek Inc.
File
9:50    Session PW3 - PW3.3: Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators
Dantu Nandini Devi1, Gandi Ajay Kumar2, Bindu G Gowda2, Madhav Rao3
1International Institute of Information Technology Bangalore, 2international institute of information technology, bangalore, 3International Institute of Information Technology-Bangalore
9:55    Session PW3 - PW3.4: An Energy-Efficient time Domain Based Compute In-Memory Architecture for Binary Neural Network
Subhradip Chakraborty1, Dinesh Kushwaha2, Abhishek Goel3, Anmol Singla4, Anand Bulusu3, Sudeb Dasgupta3
1RGIPT Uttar Pradesh, 2Student, 3IIT Roorkee, 4NIT Uttarakhand
10:00    Session PW3 - PW3.5: A multi band flexible N-path filter suited for non-contiguous channel aggregation
Chadi Jabbour
Telecom Paris
10:05    Session PW3 - PW3.6: Hardware Trojans in Quantum Circuits, Their Impacts, and Defense
Rupshali Roy1, Subrata Das2, Swaroop Ghosh1
1Pennsylvania State University, 2The Pennsylvania State University
10:10    Session PW3 - PW3.7: Thinking Outside the Clock: Physical Design for Field-coupled Nanocomputing with Deep Reinforcement Learning
Simon Hofmann, Marcel Walter, Lorenzo Servadei, Robert Wille
Technical University of Munich
10:15    Session PW3 - PW3.8: Non-parametric Greedy Optimization of Parametric Quantum Circuits
Koustubh Phalak and Swaroop Ghosh
Pennsylvania State University
10:20    Session PW3 - PW3.9: Merits of Time-Domain Computing for VMM - A Quantitative Comparison
Florian Freye1, Jie Lou1, Christian Lanius1, Tobias Gemmeke2
1Chair of Integrated Digital Systems and Circuit Design at RWTH Aachen University, 2RWTH Aachen University
10:25    Session PW3 - PW3.10: nvXNOR Design with Enhanced Store Capability for BNN Applications
Zeinab Soueidan1 and Rouwaida Kanj2
1American University of Beirut, 2Synopsys, American University of Beirut on Leave
Thursday April 4
                         Session 3A - Simulation and Estimation Automation
Chair: tbd, tbd
Co-Chair: tbd, tbd
10:45    Session 3A - 3A.1: Fast Current Constraints Generation for Chip Safety
Cedric Feghali and Farid Najm
University of Toronto
11:05    Session 3A - 3A.2: Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes
Philipp Fengler1, Sani Nassif2, Ulf Schlichtmann1
1Technical University of Munich, 2Radyalis
11:25    Session 3A - 3A.3: A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits
Teo Vallone1, Hayri Hasou2, Ernesto Colizzi2, Sara Vinco3, Davide Zoni1
1Politecnico di Milano, 2Infineon Technologies, 3Politecnico di Torino
11:45    Session 3A - 3A.4: GridVAE: Fast Power Grid EM-Aware IR Drop Prediction and Fixing Accelerated by Variational AutoEncoder
Yibo Liu and Sheldon Tan
University of Califronia, Riverside
12:05    Session 3A - 3A.5: Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model
Stavros Simoglou1, Iordanis Lilitsis2, Nikolaos Blias2, Christos Sotiriou2
1Synopsys, 2Univesity of Thessaly - Department of Electrical and Computer Engineering (EECE)
Thursday April 4
                         Session 3B - Novel Computing
Chair: Kang Jun Bai, AFRL/RITB
Co-Chair: Haowen Fang, Synopsys
10:45    Session 3B - 3B.1: An FPGA-based Max-K-Cut Accelerator Exploiting Oscillator Synchronization Model
Mohammad Khairul Bashar1, Zheyu Li2, Vijaykrishnan Narayanan2, Nikhil Shukla1
1University of Virginia, 2Pennsylvania State University
11:05    Session 3B - 3B.2: A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators
Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Alo Oluwaseun, Ishan Thakkar
University of Kentucky
11:25    Session 3B - 3B.3: A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators
Gopal Raut1, PRANOSE EDAVOOR2, DAVID SELVAKUMAR3, ritambhara thakur1
1CDAC Bangalore, 2CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING, 3C-DAC, BANGALORE
File
11:45    Session 3B - 3B.4: Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats
Mahati Basavaraju1, Vinay R1, Madhav Rao2
1International Institute of Information Technology, Bangalore, 2International Institute of Information Technology-Bangalore
Thursday April 4
                         Session 3C - AI Accelerators
Thursday April 4
                         Session 4A - Advances in Physical Design Automation
Chair: tbd, tbd
Co-Chair: tbd, tbd
14:10    Session 4A - 4A.1: Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations
Junghyun Yoon1 and Heechun Park2
1Kookmin University, School of Electrical Engineering, 2Kookmon University
14:30    Session 4A - 4A.2: Routing Intent Aware Pin Access Point Selection for Standard Cell Designs
Po-Chun Wang, Kai-Jie Ton, Rung-Bin Lin
Yuan Ze University
14:50    Session 4A - 4A.3: SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization
Joong-Won Jeon1, Andrew Kahng2, Jae-Hyun Kang1, Jaehwan Kim1, Mingyu Woo2
1Samsung Foundry, 2UCSD
15:10    Session 4A - 4A.4: Parasitic Capacitance Patterns Grid Density Binarization and Shifted Reflection Step Sequence Encoding for Dimensionality Reduction
Ping Li and guan zhong
Sun Yat-sen University
Thursday April 4
                         Session 4B - Side channel Signals in Hardwrare Security
Chair: tbd, tbd
Co-Chair: tbd, tbd
14:10    Session 4B - 4B.1: Side-channel-driven Intrusion Detection System for Mission Critical Unmanned Aerial Vehicles
Alejandro Almeida, Muneeba Asif, Md Tauhidur Rahman, Mohammad Rahman
Florida International University
14:30    Session 4B - 4B.2: Deep Learning Enhanced Side Chanel Analysis on CRYSTALS-Kyber
Tuan Hoang, Mark Kennaway, Dung Pham, Son Mai, Ayesha Khalid, Ciara Rafferty, Maire O'Neill
Queen's University Belfast
14:50    Session 4B - 4B.3: Thermo-Attack Resiliency: Addressing a New Vulnerability in Opto-Electrical Network-on-Chips
Mahdi Hasanzadeh1, Meisam Abdollahi2, Amirali Baniasadi2, Ahmad Patooghy3
1North Carolina A & T State University, 2University of Victoria, 3North Carolina A&T State University
File
15:10    Session 4B - 4B.4: Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors
Krithika Dhananjay1, Vasilis Pavlidis2, Ayse Coskun3, Emre Salman1
1Stony Brook University, 2University of Manchester, 3Boston University
15:30    Session 4B - 4B.5: TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments Authors: Quentin Forcioli, Jean-Luc Danger and Sumanta Chaudhuri
Quentin Forcioli, Sumanta Chaudhuri, Jean-luc Danger
Telecom Paris
Thursday April 4
                         Session 4C - Next Generation IoT
Friday April 5
                         Session 5A - Emerging Computing Paradigms
Chair: tbd, tbd
Co-Chair: tbd, tbd
9:00    Session 5A - 5A.1: Design and Evaluation of Parametric NTT Hardware Unit using different Multiplier based Modular Reduction Techniques
Lokesh Maji1, Aman Prajapati1, Madhav Rao2
1International Institute of Information Technology Bangalore, 2International Institute of Information Technology-Bangalore
9:20    Session 5A - 5A.2: Multi-ALM: Run-time Multi-Level Reconfigurable Approximate Logarithmic Multiplier
Maliha Tasnim, Chinmay Raje, Sheldon Tan
University of California Riverside
9:40    Session 5A - 5A.3: SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology
Dinesh Kushwaha1, Ashish Joshi2, Abhishek Goel3, Rajiv Joshi4, Sudeb Dasgupta3, Anand Bulusu3
1Student, 2Intel India, 3IIT Roorkee, 4IBM TJ Watson
10:00    Session 5A - 5A.4: Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach
Bindu G Gowda1, Prashanth H C2, Muralidhara V N3, Madhav Rao3
1International Institute of Information Technology, Bangalore, 2IIIT-Bangalore, 3International Institute of Information Technology-Bangalore
10:00    Session 5A - 5A.4: Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing
Bipul Boro, Rushik Parmar, Ashvinikumar Dongre, Gaurav Trivedi
Indian Institute of Technology Guwahati
Friday April 5
                         Session 5B - Learning on the Edge
Chair: tbd, tbd
Co-Chair: tbd, tbd
9:00    Session 5B - 5B.1: AutoAnnotate: Reinforcement Learning based Code Annotation for High Level Synthesis
Hafsah Shahzad1, Ahmed Sanaullah2, Sanjay Arora2, Ulrich Drepper2, Martin Herbordt1
1Boston University, 2RedHat Inc.
9:20    Session 5B - 5B.2: Write Intensity based Foresightful page migration for Hybrid memories
Aswathy NS1 and Hemangee Kapoor2
1IIT Guwahati, 2Indian Institute of Technology Guwahati
9:40    Session 5B - 5B.3: Real-Time Keyword Spotting based on integer arithmetic for edge deployment
Prakash Dhungana and Sayed Salehi
University of Kentucky
10:00    Session 5B - 5B.4: Bring it On: Kinetic Energy Harvesting to Spark Machine Learning Computations in IoTs
sanket shukla and Sai Manoj Pudukotai Dinakarrao
George mason university
10:20    Session 5B - 5B.5: Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology
Rupesh Karn1, Johann Knechtel2, Ozgur Sinanoglu2
1New York University, 2New York University Abu Dhabi
Friday April 5
                         Session 5C - AI for Cyber Security
Friday April 5
                         Session 6A - FAQ: FPGAs, Accelerators, Quantum
Chair: tbd, tbd
Co-Chair: tbd, tbd
10:45    Session 6A - 6A.1: Emerging Reconfigurable Logic Device Based FPGA Design and Optimization
Sheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan
The University of Texas at Arlington
11:05    Session 6A - 6A.2: A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics
Venkata Sai Praneeth Karempudi1, Sairam Sri Vatsavai1, Ishan Thakkar1, Oluwaseun Alo1, Todd Hastings1, Justin Woods2
1University of Kentucky, 2Argonne National Lab
11:25    Session 6A - 6A.3: QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization
Seongbin Kwon, Dohun Kim, Sunghye Park, Seojeong Kim, Seokhyeong Kang
Pohang University of Science and Technology
11:45    Session 6A - 6A.4: QuEST: Quantum Circuit Output Estimation using Gaussian Distribution Analysis
Shamik Kundu, Navnil Choudhury, Kanad Basu
University of Texas at Dallas
11:45    Session 6A - 6A.4: BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture
Hasita Veluri and Dilip Vasudevan
Lawrence Berkeley National Laboratory
Friday April 5
                         Session 6B - AI Accelerator Hardware Design
Chair: Hao Jiang, San Francisco State University
Co-Chair: Zhen Zhou, Intel
10:45    Session 6B - 6B.1: EASI-CiM: Event-driven asynchronous Stream-based Image Classifier with Compute-in-Memory kernels
Rahul Sreekumar1, Minseong Park1, Mohammad Nazmus Sakib1, Bhupendra Singh Reniwal2, Kyusang Lee1, Mircea Stan1
1University of Virginia, 2Indian Institute of Technology Jodhpur
11:05    Session 6B - 6B.2: Temporal-encoded 6T-RRAM with Bidirectional Control for Future Neuromorphic Systems
Kang Jun Bai1, Hao Jiang2, Jianbin Huang2, Zhaoxi Li2
1Air Force Research Laboratory, 2San Francisco State University
11:25    Session 6B - 6B.3: Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network
Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Saxena, Sudeb Dasgupta, Anand Bulusu
Indian Institute of Technology Roorkee
11:45    Session 6B - 6B.4: DESPINE: NAS generated Deep Evolutionary Adaptive Spiking Network for Low Power Edge Computing Applications
Ajay BS1 and Madhav Rao2
1IntelTechnologyIndiaPvtLtd., 2International Institute of Information Technology-Bangalore
Friday April 5
                         Session 6C - Hardware Security Primitives
Chair: tbd, tbd
Co-Chair: tbd, tbd
10:45    Session 6C - 6C.1: DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks
Yinghua Hu1, Kaixin Yang2, Subhajit Dutta Chowdhury2, Pierluigi Nuzzo2
1Synopsys, 2University of Southern California
11:05    Session 6C - 6C.2: RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation
Haimanti Chakraborty and Ranga Vemuri
University of Cincinnati
11:25    Session 6C - 6C.3: Obfuscating Quantum Hybrid-Classical Algorithms for Security and Privacy
Suryansh Upadhyay1 and Swaroop Ghosh2
1Penn State University, 2Pennsylvania State University
11:45    Session 6C - 6C.4: A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond
Rouwaida Kanj1 and Jamil Kawa2
1Synopsys (American University of Beirut, on leave), 2Synopsys