ISQED 2012: Program (Rev. 3)


SESSION 1A

Tuesday March 20 2012

Test and Measurement

Chair: Sreejit Chakravarty, LSI Corporation
Co-Chair: Srivatsa Vasudevan, Synopsys Inc.

10:20AM
1A.1
Physical-Design-Friendly Hierarchical Logic Built-In Self-Test – A Case Study
Kelvin Nelson1,  Jaga Shanmugavadivelu1,  Jayanth Mekkoth1,  Venkat Ghanta1,  Jun Wu1,  Fe Zhuang1,  Hao-Jan Chao2,  Shianling Wu2,  Jie Rao2,  Lizhen Yu2,  Laung-Terng Wang2
1Cisco Systems, 2SynTest Technologies, Inc.

10:40AM
1A.2
A Self-Testable SiGe LNA and Built-in-Self-Test Methodology for Multiple Performance Specifications of RF Amplifiers
Abhilash Goyal1,  Madhavan Swaminathan2,  Abhijit Chatterjee2,  Duane Howard2,  John Cressler2
1Oracle, Santa Clara, CA, USA, 2GaTech, Atlanta, USA

11:00AM
1A.3
Improved Path Clustering for Adaptive Path-Delay Testing
Tuck-Boon Chan and Andrew Kahng
UCSD

11:20AM
1A.4
TSV and DFT Cost Aware Circuit Partitioning for 3D-SOCs
Amit Kumar1,  Sudhakar M. Reddy1,  Irith Pomeranz2,  Bernd Becker3
1Dept. of ECE, University of Iowa, Iowa City, USA, 2School of ECE, Purdue Univ, West Lafayette, USA, 3Dept of Computer Sci, Univ of Freiburg, Freiburg, Germany

11:40AM
1A.5
A Design-For-Test Apparatus for Measuring On-Chip Temperature with Fine Granularity
James Tandon,  Masahiro Sasaki,  Makoto Ikeda,  Kunihiro Asada
University of Tokyo


SESSION 1B

Tuesday March 20 2012

Reliable System Design

Chair: Payman Zarkesh-Ha, University of New Mexico
Co-Chair: Srinivas Bodapati, Intel

10:20AM
1B.1
Wearout-Aware Compiler-Directed Register Assignment for Embedded Systems
Fahad Ahmed1,  Mohamed Sabry2,  David Atienza2,  Linda Milor1
1Georgia Institute of Technology, 2Ecole Polytechnique Federale de Lausanne

10:40AM
1B.2
Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield
Davit Mirzoyan1,  Benny Akesson2,  Kees Goossens2
1Delft University of Technology, 2Eindhoven University of Technology

11:00AM
1B.3
Single Fault Reliability Analysis in FPGA Implemented Circuits
Hadi Jahanirad1,  Karim Mohammadi1,  Pejman Attarsharghi2
1College of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran, 2Electronics Research Center, Sharif University of Technology, Tehran, Iran

11:20AM
1B.4
Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction.
Mahesh Poolakkaparambil1,  Jimson Mathew1,  Abusaleh Jabir2,  Saraju Mohanty2
1Oxford Brookes University, 2University of North Texas

11:40AM
1B.5
Delay Insensitive Code-Based Timing and Soft Error-Resilient and Adaptive-Performance Logic
Bao Liu,  Xuemei Chen,  Fiona Teshome
University of Texas at San Antonio


SESSION 1C

Tuesday March 20 2012

System Frameworks and Tools

Chair: Makram Mansour, Texas Instruments
Co-Chair: Jose Silva Matos, University of Porto

10:20AM
1C.1
Online Mapping of Embedded Applications on MPSoCs
Nasreddine Hireche and Samar Abdi
Concordia University

10:40AM
1C.2
A Particle Swarm Optimization Approach for Synthesizing Application-specific Hybrid Photonic Networks-on-Chip
Shirish Bahirat and Sudeep Pasricha
Department of Electrical and Computer Engineering, Colorado State University

11:00AM
1C.3
A Preliminary Study on System-level Impact of Persistent Main Memory
Taciano Perez1,  Ney Laert Vilar Calazans2,  Cesar A. F. De Rose2
1Hewlett Packard, 2PUCRS

11:20AM
1C.4
Optimal Microarchitectural Design Configuration Selection for Processor Hard- Error Reliability
Ying Zhang,  Lide Duan,  Bin Li,  Lu Peng
Louisiana State University

11:40AM
1C.5
Noc-based platform for embedded software design: An extension of the Hellfire Framework
Felipe Magalhães,  Oliver Longhi,  Sérgio Filho,  Alexandra Aguiar,  Fabiano Hessel
Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)


SESSION 2A

Tuesday March 20 2012

Thermal and Power in 3D ICs

Chair: Tan Yan, Synopsys, Inc.
Co-Chair: Martin Wang, UIUC

1:30PM
2A.1
Thermal Via Structural Design in Three-Dimensional Integrated Circuits
Leslie Hwang,  Kevin Lin,  Martin Wong
University of Illinois

1:50PM
2A.2
Functional Test Pattern Generation for Maximizing Temperature in 3D IC Chip Stack
Sudarshan Srinivasan and Sandip Kundu
Umass Amherst

2:10PM
2A.3
Thermal analysis of 3D integrated circuits based on discontinous Galerkin finite element method
Amir Zjajo,  Nick van der Meijs,  Rene van Leuken
Delft University of Technology

2:30PM
2A.4
Full-chip Thermal Analysis of 3D ICs with Liquid Cooling by GPU-Accelerated GMRES Method
Xue-Xin Liu,  Zao Liu,  Sheldon X.-D. Tan,  Joseph Gordon
University of California, Riverside

2:50PM
2A.5
Leakage-Aware Performance-Driven TSV-Planning Based on Network flow Algorithm in 3D ICs
Kan Wang1,  Sheqin Dong1,  Yuchun Ma1,  Goto Satoshi2,  Jason Cong3
1Tsinghua University, 2Waseda University, 3UCLA

3:10PM
2A.6
A 3D IC Designs Partitioning Algorithm with Power Consideration
Ho-Lin Chang,  Hsiang-Cheng Lai,  Tsu-Yun Hsueh,  Wei-Kai Cheng,  Mely Chen Chi
Chung Yuan Christian University


SESSION 2B

Tuesday March 20 2012

Low Power Communication Circuits

Chair: Syed Alam, Everspin Technologies Inc.
Co-Chair: Dinesh Somasekhar, Global Foundries

1:30PM
2B.1
Embracing Local Variability to Enable a Robust High-Gain Positive-Feedback Amplifier: Design Methodology and Implementation
Kareem Ragab,  Ranjit Gharpurey,  Michael Orshansky
University of Texas at Austin

1:50PM
2B.2
An Ultra-Low Voltage Digitally Controlled Low-Dropout Regulator with Digital Background Calibration
Yongtae Kim and Peng Li
Texas A&M University

2:10PM
2B.3
Dynamically biased low power High performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process
Karthik Rajagopal
Texas Instruments

2:30PM
2B.4
Design of an Efficient NoC Architecture using Millimeter-Wave Wireless Links
Sujay Deb1,  Kevin Chang1,  Amlan Ganguly2,  Xinmin Yu1,  Partha Pande1,  Christof Teuscher3,  Deuk Heo1,  Benjamin Belzer1
1Washington State University, 2Rochester Institute of Technology, 3Portland State University

2:50PM
2B.5
A Novel Robust Signaling Scheme for High-Speed Low-Power Communication over Long Wires
Marshnil Dave,  Maryam Shojaei Baghini,  Dinesh Sharma
IIT-Bombay

3:10PM
2B.6
An Extended-Range Incremental CT Sigma Delta ADC with Optimized Digital Filter
Julian Garcia and Ana Rusu
KTH Royal Institute of Technology


SESSION 2C

Tuesday March 20 2012

Process-Induced Variability & Hot Spot Detection

Chair: Rajan Beera, Texas Instruments
Co-Chair: Valeriy Sukharev, Mentor Graphics

1:30PM
2C.1
Test Structure, Circuits and Extraction Methods to Determine the Radius of Influence of STI and Polysilicon Pattern Density
Albert H. Chang1,  Kewei Zuo2,  Jean Wang2,  Douglas Yu2,  Duane Boning1
1Massachusetts Institute of Technology, 2Taiwan Semiconductor Manufacturing Company, Ltd.

1:50PM
2C.2
Post-Placement Lithographic Hotspot Detection and Removal in One-Dimensional Gridded Designs
Jen-Yi Wuu1,  Mark Simmons2,  Malgorzata Marek-Sadowska1
1University of California, Santa Barbara, 2Mentor Graphics Corporation

2:10PM
2C.3
On Lithography Aware Metal-Fill Insertion
Vikram Suresh,  Priyamvada Vijayakumar,  Sandip Kundu
University of Massachusetts, Amherst

2:30PM
2C.4
Understanding, Modeling, and Detecting Pooling Hotspots in Copper CMP
Aaron Gower-Hall1,  Tamba Gbondo-Tugbawa1,  JenPin Weng1,  Wei-tsu Tseng2,  Laertis Economikos2,  Toshiaki Yanagisawa2,  Pavan Bashaboina2,  Stephen Greco2
1Cadence Design Systems, 2IBM Semiconductor Research and Development Center

2:50PM
2C.5
Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance
Li Yu1,  Wen-Yao Chang2,  Kewei Zuo2,  Jean Wang2,  Douglas Yu2,  Duane Boning1
1Microsystems Technology Laboratories, Massachusetts Institute of Technology, 2Taiwan Semiconductor Manufacturing Company, Ltd.

3:10PM
2C.6
High Performance Electrical Driven Hotspot Detection Solution for Full Chip Design using a Novel Device Parameter Matching Technique
Rami Fathy1,  Mohamed Al-Imam1,  Abdelrahman ElMously1,  Haitham Eissa1,  Ahmed Arafa1,  Mohab Anis2
1Mentor Graphics, 2American University in Cairo


SESSION 3A

Tuesday March 20 2012

Emerging Topics in EDA

Chair: James Lei, Applied Harmonics Corporation
Co-Chair: Anand Iyer, AMD

3:50PM
3A.1
Fast Delay Estimation with Buffer Insertion for Through-Silicon-Via-Based 3D Interconnects
Young-Joon Lee and Sung Kyu Lim
Georgia Institute of Technology

4:10PM
3A.2
Functional Composition: A New Paradigm for Performing Logic Synthesis
Mayler Martins,  Renato Ribas,  Andre Reis
UFRGS

4:30PM
3A.3
A New Voltage Binning Technique for Yield Improvement Based on Graph Theory
Ruijing Shen,  Sheldon X.-D. Tan,  Xue-Xin Liu
University of California, Riverside

4:50PM
3A.4
A Complete Power Estimation Methodology for DSP Blocks in FPGAs
Hassan Hassan and Nizar Abdallah
Microsemi Corp.

5:10PM
3A.5
Process Variation Aware DRAM Design Using Block Based Adaptive Body Biasing Algorithm
Satyajit Desai,  Sanghamitra Roy,  Koushik Chakraborty
Utah State University


SESSION 3B

Tuesday March 20 2012

Design & Analysis of Emerging Devices

Chair: Paul Tong, Pericom Semiconductor
Co-Chair: Bao Liu, University of Texas

3:50PM
3B.1
Device- and System-Level Performance Modeling for Graphene P-N Junction Logic
Chenyun Pan and Azad Naeemi
Georgia Institute of Technology

4:10PM
3B.2
Quasi-Planar Tri-gate (QPT) Bulk CMOS Technology for Single-Port SRAM Application
Yasumasa Tsukamoto1,  Makoto Yabuuchi1,  Hidehiro Fujiwara1,  Koji Nii1,  Changhwan Shin2,  Tsu-Jae King Liu3
1Renesas Electronics Corporation, 2University of Soeul, 3University of California at Berkeley

4:30PM
3B.3
A Body-Voltage-Sensing-Based Short Pulse Reading Circuit for Spin-Torque Transfer RAMs (STT-RAMs)
Fengbo Ren,  Henry Park,  Richard Dorrance,  Yuta Toriyama,  C.-K. Ken Yang,  Dejan Marković
Department of Electrical Engineering, University of California, Los Angeles, CA, USA

4:50PM
3B.4
Interconnect analysis in spin-torque devices: performance modeling, optimal repeater insertion, and circuit-size limits
Shaloo Rakheja and Azad Naeemi
Georgia Institute of Technology

5:10PM
3B.5
Analysis of Crosstalk Delay and Area for MWNT and Bundled SWNT in Global VLSI Interconnects
Manoj Kumar Majumder,  Nisarg D. Pandya,  Brajesh Kumar Kaushik,  Sanjeev Kumar Manhas
Department of Electronics and Computer Engineering, Indian Institute of Technology Roorlee


SESSION 3C

Tuesday March 20 2012

Variation-Aware Design Methodologies

Chair: Rajesh Garg, Intel
Co-Chair: Riaz Naseer, Intel

3:50PM
3C.1
Robust Metastability-based TRNG Design in Nanometer CMOS with Sub-Vdd Pre-charge and Hybrid Self-calibration
Vikram Suresh and Wayne Burleson
University of Massachusetts, Amherst

4:10PM
3C.2
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices
Takashi Sato,  Hiromitsu Awano,  Hirofumi Shimizu,  Hiroshi Tsutsui,  Hiroyuki Ochi
Kyoto Univ.

4:30PM
3C.3
Error Mitigation in Digital Logic using a Feedback Equalization with Schmitt Trigger (FEST) Circuit
Zafar Takhirov,  Bobak Nazer,  Ajay Joshi
Boston University

4:50PM
3C.4
The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter
Hu Xu1,  Vasilis F. Pavlidis1,  Wayne Burleson2,  Giovanni De Micheli1
1EPFL, 2University of Massachusetts Amherst

5:10PM
3C.5
TDDB-Based Performance Variation of Combinational Logic in Deeply Scaled CMOS Technology
Haiqing Nan,  Li Li,  Ken Choi
Illinois Institute of Technology


SESSION P

Tuesday March 20 2012

Poster Session & Mixer

Chair: Mark Budnik, Valpraiso University
Co-Chair: Keith Bowman, Intel

5:30PM
P.1
Critical Area Driven Dummy Fill Insertion to Improve Manufacturing Yield
Nishant Dhumane and Sandip Kundu
University of Massachusetts, Amherst

5:30PM
P.3
Impact of Transistor Aging Effects on Sense Amplifier Reliability in Nano-Scale CMOS
Roberto Menchaca and Hamid Mahmoodi
San Francisco State University

5:30PM
P.4
A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop
Riadul Islam
Concordia University

5:30PM
P.5
A Scalable Curve-fit Model of the Substrate Coupling Resistances for IC Design
Vijaya Kumar Gurugubelli and Shreepad Karmalkar
Indian Institute of Technology Madras

5:30PM
P.6
Efficient Reduction Techniques for Statistical Model Generation of Standard Cells
Sachin Shrivastava and Harindranath Parameswaran
Cadence Design Systems

5:30PM
P.7
Efficient Electro-Thermal Co-analysis on CPU+GPU Heterogeneous Architecture
Kun Huang,  Xu Yang,  Guoxing Zhao,  Zuying Luo
College of Information Science and Technology, Beijing Normal University

5:30PM
P.8
Dynamic Range Estimation for Systems with Control-flow Structures
Bin Wu
AMD

5:30PM
P.9
Comparison of Variations in MOSFET versus CNFET in Gigascale Integrated Systems
Ali Arabi M. Shahi,  Payman Zarkesh-Ha,  Mirza Elahi
University of New Mexico

5:30PM
P.10
Vertical Slit Field Effect Transistor in Ultra-Low Power Applications
Xiang Qiu1,  Malgorzata Marek-Sadowska1,  Wojciech Maly2
1University of California, Santa Barbara, 2Carnegie Mellon University

5:30PM
P.11
Design and Optimization of Power Gating for DVFS Applications
Tong Xu and Peng Li
Texas A&M University

5:30PM
P.12
An Area Efficient On-Chip Hybrid Voltage Regulator
Selcuk Kose1,  Sally Pinzon2,  Bruce McDermott2,  Simon Tam3,  Eby Friedman1
1University of Rochester, 2Eastman Kodak, 3Intel Corporation

5:30PM
P.13
Device and electromagnetic co-simulation of TSV: substrate noise study and compact modeling of a TSV in a matrix.
Patrick Le Maitre,  Melanie Brocard,  Alexis Farcy,  Jean-Claude Marin
STMicroelectronics

5:30PM
P.14
A Case for 3D Stacked Analog Circuits in High-Speed Sensing Systems
Mohammad Abdel-Majeed,  Mike S.W. Chen,  Murali Annavaram
University of Southern California

5:30PM
P.15
A DyadicCluster method used for Nonlinear Placement
Wenchao Gao1,  Qiang Zhou1,  Xu Qian2,  Yici Cai1
1Tsinghua University, Beijing, 2China University of Mining and Technology, Beijing

5:30PM
P.16
Clock Mesh Framework
Pinaki Chakrabarti1,  Vikram Bhatt2,  Dwight Hill3,  Aiqun Cao3
1Synopsys Inc., Bangalore, India, 2University of California, San Diego, CA, USA, 3Synopsys Inc., Mountain View, CA, USA

5:30PM
P.17
Placement Aware Clock Gate Cloning and Redistribution Methodology
Vishweshwara Ramamurthy,  Mahita Nagabhiru,  Venkatraman Ramakrishnan
Texas Instruments India

5:30PM
P.18
Impact of C-Elements in Asynchronous Circuits
Matheus Moreira,  Bruno Oliveira,  Fernando Moraes,  Ney Calazans
PUCRS

5:30PM
P.19
A Top-Down Design Methodology using Virtual Platforms for Concept Development
Mohit Shah1,  Brian Mears2,  Chaitali Chakrabarti1,  Andreas Spanias1
1Arizona State University, 2Intel Corporation

5:30PM
P.20
Partitioning and Dynamic Mapping Evaluation for Energy Consumption Minimization on NoC-Based MPSoC
Eduardo Antunes,  Matheus Soares,  Alexandra Aguiar,  Sergio Johann F.,  Marcos Sartori,  Fabiano Hessel,  Cesar Marcon
PUCRS


SESSION 4A

Wednesday March 21, 2012

Physical Design

Chair: Makoto Ikeda, University of Tokyo
Co-Chair: Martin Wang, UIUC

10:20AM
4A.1
Ordinary Kriging Metamodel-Assisted Ant Colony Algorithm for Fast Analog Design Optimization
Oghenekarho Okobiah,  Saraju Mohanty,  Elias Kougianos
University of North Texas

10:40AM
4A.2
CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects
Yu Zhang,  Bo Liu,  Bo Yang,  Jing Li,  Shigetoshi Nakatake
The University of Kitakyushu

11:00AM
4A.3
DRC-Free High Density Layout Exploration with Layout Morphing and Patterning Quality Assessment, with Application to SRAM
Amith Singhee1,  Emrah Acar1,  Mohammad Younus2,  Rama Singh3,  Aditya Bansal1
1IBM T J Watson Research Center, 2IBM Corporation, 3

11:20AM
4A.4
Hierarchical Power Network Synthesis for Multiple Power Domain Designs
Chieh-Jui Lee1,  Sean Shih-Ying Liu1,  Chuan-Chia Huang1,  Hung-Ming Chen1,  Chang-Tzu Lin2,  Chia-Hsin Lee2
1National Chiao Tung University, 2Industrial Technology Research Institute

11:40AM
4A.5
Algorithmic Study on the Routing Reliability Problem
Qiang Ma,  Zigang Xiao,  Martin D. F. Wong
University of Illinois at Urbana-Champaign


SESSION 4B

Wednesday March 21, 2012

Robust SRAM Design

Chair: Srinivas Bodapati, Intel
Co-Chair: Hamid Mahmoodi, SFSU

10:20AM
4B.1
A 40-nm 256-Kb 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique Enabling 367-mV VDDmin Reduction
Masaharu Terada1,  Shusuke Yoshimoto1,  Shunsuke Okumura1,  Toshikazu Suzuki2,  Shinji Miyano2,  Hiroshi Kawaguchi1,  Masahiko Yosimoto1
1Kobe University, 2Semiconductor Technology Academic Research Center (STARC)

10:40AM
4B.2
Process Variation Tolerant 9T SRAM Bitcell Design
G K Reddy and jawar singh
Jaypee University of Engineering & Technology

11:00AM
4B.3
History & Variation Trained Cache (HVT-Cache) A Process Variation Aware and Fine Grain voltage Scalable Cache with Active Access History Monitoring
Avesta Sasan1,  Houman Homayoun2,  Kiarash Amiri3,  Ahmed Eltawil3,  Fadi Kurdahi3
1Broadcom, 2University of California San Diego, 3University of California Irvine

11:20AM
4B.4
VAR-TX: A Variability-Aware SRAM Model for Predicting the Optimum Architecture to achieve Minimum Access-Time for Yield Enhancement in Nano-scaled CMOS
Jeren Samandari-Rad,  Matthew Guthaus,  Richard Hughey
University of California, Santa Cruz

11:40AM
4B.5
Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation
Yuki Kagiyama,  Shunsuke Okumura,  Koji Yanagida,  Shusuke Yoshimoto,  Yohei Nakata,  Shintaro Izumi,  Hiroshi Kawaguchi,  Masahiko Yoshimoto
Kobe University


SESSION 4C

Wednesday March 21, 2012

3D Effects on Package Co-Design

Chair: Kamesh Gadepally, Texas Instruments
Co-Chair: Lalitha Immaneni, Intel

10:20AM
4C.1
Invited Paper 4C.1
Keith Bowman
Intel

10:40AM
4C.2
Chip-Package Power Delivery Network Resonance Analysis and Co-design Using Time and Frequency Domain Analysis Techniques
Jonathan Watkins1,  Jai Pollayil2,  Calvin Chow2,  Aveek Sarkar2
1Maxim, 2Apache Design Inc

11:00AM
4C.3
Maintaining Power Integrity by Damping the Cavity-Mode Anti-Resonances’ Peaks on a Power Plane by Particle Swarm Optimization
Jai Narayan Tripathi1,  Raj Kumar Nagpal2,  Nitin Kumar Chhabra3,  Rakesh Malik3,  Jayanta Mukherjee1
1Department of EE, IIT Bombay., 2CEC, STMicroelectronics Pvt. Ltd, Greater Noida, INDIA, 3TRnD, STMicroelectronics Pvt. Ltd, Greater Noida, INDIA

11:20AM
4C.4
A Design Tradeoff Study with Monolithic 3D Integration
Chang Liu and Sung Kyu Lim
Georgia Institute of Technology

11:40AM
4C.5
Cost-minimized Double Die DRAM Packaging for Ultra-High Performance DDR3 and DDR4 Multi-Rank Server DIMMs
Richard Crisp1,  Bill Gervasi2,  Wael Zohni1,  Bel Haba3
1Invensas Corp, 2Discobolus Designs, 3Tessera Inc.


SESSION 5A

Wednesday March 21, 2012

Advanced Analysis & Characterization for Sub-Micron Design

Chair: Masahiro Fujita, University of Tokyo
Co-Chair: Anand Iyer, AMD

1:30PM
5A.1
Speed-path Analysis for Multi-path Failed Latches with Random Variation
Tsutomu Ishida1,  Izumi Nitta1,  Katsumi Homma1,  Yuzi Kanazawa1,  Hiroaki Komatsu2
1Fujitsu Labs. Ltd., 2Fujitsu Ltd.

1:50PM
5A.2
HiSIM-RP: A Reverse-Profiling Based 1st Principle Compact MOSFET Model and Its Application to Variability Analysis of 90nm and 40nm CMOS
Hironori Sakamoto1,  Shigetaka Kumashiro1,  Shigeo Sato2,  Naoki Wakita3,  Tohru Mogami4
1Renesas Electronics Corp., 2Fujitsu Semiconductor Ltd., 3Toshiba Corp., 4NEC Corp.

2:10PM
5A.3
An Accurate Current Source Model for CMOS Based Combinational Logic Cell
Baljit Kaur,  Sandeep Vundavalli,  Sanjeev Kumar Manhas,  Sudeb Dasgupta,  Anand Bulusu
Indian Institute of Technology, Roorkee

2:30PM
5A.4
Efficient Approaches to Overcome Non-Convexity Issues in Analog Design Automation
Supriyo Maji and Pradip Mandal
IIT Kharagpur

2:50PM
5A.5
Optimization of Importance Sampling Monte Carlo using Consecutive Mean-shift Method and its Application to SRAM Dynamic Stability Analysis
Takeshi Kida,  Yasumasa Tsukamoto,  Yuji Kihara
Renesas Electronics Corporation

3:10PM
5A.6
Metamodel-Assisted Ultra-Fast Memetic Optimization of a PLL for WiMax and MMDS Applications
Oleg Garitselov,  Saraju Mohanty,  Elias Kougianos,  Oghenekarho Okobiah
University of North Texas


SESSION 5B

Wednesday March 21, 2012

Power-Aware Design

Chair: Cheng Zhuo, Intel
Co-Chair: Mark Budnik, Valpraiso University

1:30PM
5B.1
24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage Domains in VDDmin Limited Ultra Low Voltage Logic Circuits
Tadashi Yasufuku1,  Koji Hirairi2,  Yu Pu1,  Yun Fei Zheng1,  Ryo Takahashi1,  Masato Sasaki1,  Hiroshi Fuketa1,  Atsushi Muramatsu2,  Masahiro Nomura2,  Hirofumi Shinohara2,  Makoto Takamiya1,  Takayasu Sakurai1
1University of Tokyo, 2Semiconductor Technology Academic Research Center

1:50PM
5B.2
Enhancing Efficiency and Robustness of a Photovoltaic Power System under Partial Shading
Yanzhi Wang1,  Xue Lin1,  Younghyun Kim2,  Naehyuck Chang2,  Massoud Pedram1
1University of Southern California, 2Seoul National University

2:10PM
5B.3
Comparison between power gating and DVFS from the view point of energy efficiency
Atsuki Inoue
Fujitsu Lab. Ltd.

2:30PM
5B.4
Design of Low-Power, Scalable-Throughput Systems at Near/Sub Threshold Voltage
Meeta Srivastav,  Michael Henry,  Leyla Nazhandali
Virginia Tech University

2:50PM
5B.5
Analysis and Evaluation of Greedy Thread Swapping Based Dynamic Power Management for MPSoC Platforms
Chirag Ravishankar1,  Sundaram Ananthanaryanan2,  Siddharth Garg1,  Andrew Kennings1
1University of Waterloo, 2University of Waterloo/Anna University

3:10PM
5B.6
Efficient Leakage Power Saving by Sleep Depth Controlling for Multi-mode Power Gating
Seidai Takeda1,  Shinobu Miwa1,  Kimiyoshi Usami2,  Hiroshi Nakamura1
1The University of Tokyo, 2Shibaura Institute of Technology


SESSION 5C

Wednesday March 21, 2012

Circuit-Level Variability & Manufacturability

Chair: Shubhankar Basu, Global Foundries
Co-Chair: Saraju Mohanty, University of North Texas

1:30PM
5C.1
DDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators
Tuck-Boon Chan1,  Puneet Gupta2,  Andrew Kahng1,  LiangZhen Lai2
1UCSD, 2UCLA

1:50PM
5C.2
An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design
Samatha Gummalla,  Anupama R Subramaniam,  Chaitali Chakrabarti,  Yu (kevin) Cao
Arizona State University

2:10PM
5C.3
Process Mismatch Analysis based on Reduced-Order Models
Mustafa B Yelten,  Paul D Franzon,  Michael B Steer
North Carolina State University

2:30PM
5C.4
Transistor Channel Decomposition for Structured Analog Layout, Manufacturability and Low-power Applications
Qing Dong,  Bo Yang,  Gong Chen,  Jing Li,  Shigetoshi Nakatake
The University of Kitakyushu, Japan

2:50PM
5C.5
Theory of Redundancy for Logic Circuits to Maximize Yield/Area
Mohammad Mirza-Aghatabar,  Melvin A. Breuer,  Sandeep K. Gupta,  Shahin Nazarian
University of Southern California

3:10PM
5C.6
A Novel Sample Reuse Methodology for Fast Statistical Simulations with Applications to Manufacturing Variability
Rouwaida Kanj1 and Rajiv Joshi2
1American University of Beirut - on IBM Leave, 2IBM


SESSION 6A

Wednesday March 21, 2012

Verification & Silicon Debug

Chair: Srivatsa Vasudevan, Synopsys Inc.
Co-Chair: Sreejit Chakravarty, LSI Corporation

3:50PM
6A.1
Monitoring and Timing Prediction in Early Analyzing and Checking Performance of Interconnection Networks at ESL
Mao-Yin Wang and Jen-Chieh Yeh
Information & Communications Research Laboratories, Industrial Technology Research Institute

4:10PM
6A.2
Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams
Anton Karputkin,  Raimund Ubar,  Mati Tombak,  Jaan Raik
Tallinn University of Technology

4:30PM
6A.3
Assertion Clustering for Compacted Test Sequence Generation
Jason Tong1,  Marc Boulé2,  Dr. Zeljko Zilic1
1McGill University, 2École de Technologie Supérieure

4:50PM
6A.4
Transaction-Based Post-Silicon Debug of Many-Core System-on-Chips
Amir Masoud Gharehbaghi and Masahiro Fujita
University of Tokyo

5:10PM
6A.5
An Enhanced Debug-Aware Network Interface for Network-on-Chip
M. H. Neishaburi and Zeljko Zilic
McGill University


SESSION 6B

Wednesday March 21, 2012

Challenges & Opprotunities in New Technologies

Chair: Paul Tong, Pericom Semiconductor
Co-Chair: Bao Liu, University of Texas

3:50PM
6B.1
Process Induced Mechanical Stress Aware Poly-Pitch Optimization for Enhanced Circuit Performance
Naushad Alam,  Sudeb Dasgupta,  Bulusu Anand
Indian Institute of Technology Roorkee, India

4:10PM
6B.2
Design Issues and Insights of Multi-Fin Bulk Silicon FinFETs
Hsun Li and Meng-Hsueh Chiang
National Ilan University

4:30PM
6B.3
Self-Heating Effects in Gate-all-around Silicon Nanowire MOSFETs: Modeling and Analysis
Xin Huang,  Tianwei Zhang,  Runsheng Wang,  Changze Liu,  Yuchao Liu,  Ru Huang
Institute of Microelectronics, Peking University

4:50PM
6B.4
Comparison of Electrical, Optical and Plasmonic On-Chip Interconnects Based on Delay and Energy Considerations
Shaloo Rakheja and Vachan Kumar
Georgia Institute of Technology

5:10PM
6B.5
Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices
Kaiyuan Yang1,  Dae Hyun Kim2,  Sung Kyu Lim2
1Tsinghua University, 2Georgia Institute of Technology


SESSION 6C

Wednesday March 21, 2012

Energy-Aware System Design

Chair: Lech Jozwiak, Eindhoven University of Technology
Co-Chair: Rajesh Berigei, Texas Instruments

3:50PM
6C.1
Learning Based DVFS for Simultaneous Temperature, Performance and Energy Management
Hao Shen1,  Jun Lu2,  Qinru Qiu1
1Syracuse University, 2Binghamton University

4:10PM
6C.2
Hot Peripheral Thermal Management to Mitigate Cache Temperature Variation
Houman Homayoun1,  Mehryar Rahmatian2,  Vasileios Kontoniris1,  Shahin Golshan2,  Dean Tullsen1
1University of California San Diego, 2University of California Irvine

4:30PM
6C.3
Power-Performance Yield Optimization for MPSoCs Using MILP
Kshitij Bhardwaj,  Sanghamitra Roy,  Koushik Chakraborty
Utah State University

4:50PM
6C.4
A Variation and Energy Aware ILP formulation for Task Scheduling in MPSoC
Mahboobeh Ghorbani
University of Southern California

5:10PM
6C.5
Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis
Keisuke Inoue and Mineo Kaneko
Japan Advanced Institute of Science and Technology