International Symposium on Quality Electronic Design (ISQED)
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ISQED 2011 Program

SESSION 1A

Tuesday March 15 2011

 

Device Aging: Analysis and Design

Chair: Hamid Mahmoodi
Co-Chair: Srinivas Bodapati

 

10:20AM
1A.1
Analysis and Mitigation of NBTI Aging in Register File: An End-To-End Approach
Saurabh Kothawade,  Koushik Chakraborty,  Sanghamitra Roy
Utah State University

 

10:40AM
1A.2
Reducing Impact of Degradation on Analog Circuits by Chopper Stabilization and Autozeroing
Shailesh More1,  Michael Fulde2,  Florian Chouard1,  Doris Schmitt-Landsiedel1
1Institute for Technical Electronics, Technical University of Munich, Germany, 2Infineon Technologies AG, Villach, Austria

 

11:00AM
1A.3
Circuit-level delay modeling considering both TDDB and NBTI
Hong Luo1,  Xiaoming Chen1,  Jyothi Velamala2,  Yu Wang1,  Yu Cao2,  Vikas Chandra3,  Yuchun Ma4,  Huazhong Yang1
1Dept. of E.E., TNList, Tsinghua Univ., Beijing, China, 2Dept. of E.E., Arizona State Univ., USA, 3ARM R&D, San Jose, USA, 4Dept. of C.S., TNList, Tsinghua Univ., Beijing, China

 

11:20AM
1A.4
Modeling of Random Telegraph Noise under Circuit Operation - Simulation and Measurement of RTN-induced delay fluctuation -
Kyosuke Ito1,  Takashi Matsumoto1,  Shinichi Nishizawa1,  Hiroki Sunagawa1,  Kazutoshi Kobayashi2,  Hidetoshi Onodera3
1Kyoto University, 2Kyoto Institute of Technology, 3Kyoto University, JST, CREST

 

11:40AM
1A.5
Modeling and Analyzing NBTI in the Presence of Process Variation
Taniya Siddiqua,  Sudhanva Gurumurthi,  Mircea Stan
University of Virginia

 

 


 

SESSION 1B

Tuesday March 15 2011

 

Analog and 3D Integrated Circuits

Chair: Martin Wong
Co-Chair: Vamsi Srikantam

 

10:20AM
1B.1
A Novel Detailed Routing Algorithm with Exact Matching Constraint for Analog and Mixed Signal Circuits
Qiang Gao,  Hailong Yao,  Qiang Zhou,  Yici Cai
Tsinghua University

 

10:40AM
1B.2
Signal Integrity Analysis and Optimization for 3D ICs
Chang Liu1,  Taigon Song1,  Sung Kyu Lim2
1Georgia Institute of Technology, 2Georgia Institue of Technology

 

11:00AM
1B.3
3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation
Cheng-Chi Chan,  Yen-Ting Yu,  Iris Hui-Ru Jiang
National Chiao Tung University

 

11:20AM
1B.4
Accurate Analysis of Substrate Sensitivity of Active Transistors in an Analog Circuit
Satoshi Takaya1,  Yoji Bando1,  Toru Ohkawa2,  Toshiharu Takaramoto2,  Toshio Yamada2,  Masaaki Souda2,  Shigetaka Kumashiro2,  Tohru Mogami2,  Makoto Nagata1
1Kobe University, 2MIRAI-Selete

 

11:40AM
1B.5
Full-Chip Analysis of Unintentional Forward Biased Diodes
Amir Grinshpon1,  Adam Segoli Schubert1,  Ziyang Lu2
1Freescale Semiconductor, 2Mentor Graphics

 

 


 

SESSION 1C

Tuesday March 15 2011

 

Low Power Circuits, Sensors, and Memories

Chair: Syed Alam
Co-Chair: Mark Budnik

 

10:20AM
1C.1
A 12.4μm^2 133.4μW 4.56mV/C Resolution Digital On-Chip Thermal Sensing Circuit in 45nm CMOS Utilizing Sub-Threshold Operation
Basab Datta and Wayne Burleson
University of Massachusetts-Amherst

 

10:40AM
1C.2
Effective Algorithm for Integrating Clock Gating and Power Gating to Reduce Dynamic and Active Leakage Power Simultaneously
Li Li,  Ken Choi,  Haiqing Nan
Illinois Institute of Technology

 

11:00AM
1C.3
Transient and Fine-Grained Voltage Adaptation for Variation Resilience in VLSI Interconnects
Kyu-Nam Shim and Jiang Hu
ECE, Texas A&M University, College Station, TX

 

11:20AM
1C.4
A 128kb High Density Portless SRAM Using 
Hierarchical Bitlines and Thyristor Sense Amplifiers
Michael Wieckowski,  Gregory Chen,  Daeyeon Kim,  Dennis Sylvester,  David Blaauw
University of Michigan

 

11:40AM
1C.5
Temperature Aware Energy Management for Real-Time Scheduling
Nikhil Gupta and Rabi Mahapatra
Texas A&M University

 

 


 

SESSION 2A

Tuesday March 15 2011

 

Lithography and 3D Integration

Chair: Siddharth Garg
Co-Chair: Rajan Beera

 

1:30PM
2A.2
Coupling Timing Objectives with Optical Proximity Correction for Improved Timing Yield
Shayak Banerjee1,  Kanak Agarwal1,  Sani Nassif1,  James Culp2,  Lars Liebmann2,  Michael Orshansky3
1IBM Research, 2IBM Microelectronics, 3University of Texas - Austin

 

1:50PM
2A.3
Self-Aligned Double Patterning (SADP) Layout Decomposition
Minoo Mirsaeedi1,  J. Andres Torres2,  Mohab Anis3
1University of Waterloo, 2Mentor Graphics Corp., 3The American University of Cairo

 

2:10PM
2A.4
DFM: Impact Analysis in a High Performance Design
Stalin SM,  Amit Brahme,  Venkatraman Ramakrishnan,  Ajoy Mandal
Texas Instruments (India) Pvt. Ltd.

 

2:30PM
2A.4
Metrics for Characterizing Machine Learning-Based Hotspot Detection Methods
Jen-Yi Wuu1,  Fedor Pikus2,  Malgorzata Marek-Sadowska1
1University of California, Santa Barbara, 2Mentor Graphics Corporation

 

2:50PM
2A.5
Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs
Taigon Song1,  Chang Liu1,  Dae Hyun Kim1,  Jonghyun Cho2,  Joohee Kim2,  Jun So Pak2,  Seungyoung Ahn2,  Joungho Kim2,  Kihyun Yoon3,  Sung Kyu Lim1
1Georgia Tech ECE, 2KAIST EE, 3Silicon Image

 

3:10PM
2A.6
3D Stacked IC Layout Considering Bond Pad Density and Doubling for Manufacturing Yield Improvement
Ding-Ming Kwai and Chang-Tzu Lin
Industrial Technology Research Institute

 

 


 

SESSION 2B

Tuesday March 15 2011

 

New Ideas in Digital Design Automation

Chair: James Lei
Co-Chair: Jin He

 

1:30PM
2B.1
Invited Paper form EDA (Session 2B)
TBA TBA
TBA

 

1:50PM
2B.2
SCPlace: A Statistical Slack-Assignment Based Constructive Placer
Evriklis Kounalakis and Christos Sotiriou
FORTH-ICS, Heraklion, Crete, Greece; and University of Crete, Heraklion

 

2:10PM
2B.3
Application-Specific Network-on-Chip Synthesis: Cluster Generation and Network Component Insertion
Wei Zhong1,  Bei Yu2,  Song Chen1,  Takeshi Yoshimura1,  Sheqin Dong2,  Satoshi Goto1
1Graduate School of IPS, Waseda University, Japan., 2Department of Computer Science & Technology, Tsinghua University, China.

 

2:30PM
2B.4
Novel and Efficient Min Cut based Voltage Assignment In Gate Level
Tao Lin1,  Sheqin Dong1,  Song Chen2,  Yuchun Ma1,  Ou He1,  Satoshi Goto2
1Tsinghua university, 2Waseda university

 

2:50PM
2B.5
Multi-Objective Optimization Techniques for VLSI Circuits
Fatemeh Kashfi,  Safar Hatami,  Massoud Pedram
University of Southern California

 

 


 

SESSION 2C

Tuesday March 15 2011

 

System Frameworks and Tools

Chair: Makram Mansour
Co-Chair: Sudeep Pasricha

 

1:30PM
2C.1
A Design Time Simulator for Computer Architects
Sangeetha Sudhakrishnan1,  Francisco J. Mesa Martinez2,  Jose Renau2
1University of California, Santa Cruz, 2Univeristy of California, Santa Cruz

 

1:50PM
2C.2
Constraint Generation for Software-Based Post-Silicon Bug Masking with Scalable Resynthesis Technique for Constraint Optimization
Chia-Wei Chang1,  Hong-Zu Chou2,  Kai-Hui Chang3,  Jie-Hong Roland Jiang2,  Chien-Nan Jimmy Liu1,  Chiu-Han Hsiao4,  Sy-Yen Kuo5
1Electrical Engineering Department, National Central University, Jhongli, Taiwan, 2Electrical Engineering Department, National Taiwan University, Taipei, Taiwan, 3Avery Design Systems, Inc., Andover, MA, USA, 4Department of Information Management, National Taiwan University, Taipei, Taiwan, 5lectrical Engineering Department, National Taiwan University, Taipei, Taiwan

 

2:10PM
2C.3
POSEIDON: A Framework for Application-Specific Network-on-Chip Synthesis for Heterogeneous Chip Multiprocessors
Soohyun Kwon1,  Sudeep Pasricha2,  Jeonghun Cho1
1Kyungpook National University, 2Colorado State University

 

2:30PM
2C.4
A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling
Mineo Kaneko
Japan Advanced Institute of Science and Technology

 

2:50PM
2C.5
Virtual Hellfire Hypervisor: Extending Hellfire Framework for Embedded Virtualization Support
Alexandra Aguiar and Fabiano Hessel
PUCRS

 

3:10PM
2C.6
A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip
Sudeep Pasricha and Yong Zou
Colorado State University

 

 


 

SESSION 3A

Tuesday March 15 2011

 

Variation and Noise-Aware Design

Chair: Payman Zarkesh-Ha
Co-Chair: Riaz Nasseer

 

3:50PM
3A.1
Integrated Circuit-Architectural Framework for PSN Aware Floorplanning in Microprocessors
Mandar Padmawar1,  Sanghamitra Roy2,  Koushik Chakraborty2
1AES Corporation, 2Utah State University

 

4:10PM
3A.2
0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM
Hiroki Noguchi1,  Shunsuke Okumura1,  Tomoya Takagi1,  Koji Kugata1,  Masahiko Yoshimoto2,  Hiroshi Kawaguchi1
1Kobe University, 2Kobe University, JST CREST

 

4:30PM
3A.3
Power-Supply-Network Design in 3D Integrated Systems
Michael B Healy and Sung Kyu Lim
Georgia Institute of Technology

 

4:50PM
3A.4
An Automated Design Methodology for Yield Aware Analog Circuit Synthesis in Submicron Technology
Sabyasachi Deyati and Pradip Mandal
Indian Institute of Technology , Kharagpur

 

5:10PM
3A.5
Process Variation Sensitivity of the Rotary Traveling Wave Oscillator
Ying Teng and Baris Taskin
Drexel University

 

 


 

SESSION 3B

Tuesday March 15 2011

 

Physical Design Issues in Custom Circuits and FPGAs

Chair: Martin Wong
Co-Chair: Vamsi Srikantam

 

3:50PM
3B.1
Enhancement of Incremental Design for FPGAs Using Circuit Similarity
Xiaoyu Shi1,  Dahua Zeng1,  Yu Hu2,  Guohui Lin1,  Osmar Zaiane1
1Department of Computing Science, University of Alberta, 2Department of Electrical and Computer Engineering, University of Alberta

 

4:10PM
3B.2
On Discovery of “Missing” Physical Design Rules via Diagnosis of Soft-faults
Aswin Sreedhar and Sandip Kundu
University of Massachusetts at Amherst

 

4:30PM
3B.3
Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures
Meng-Chen Wu,  Hung-Ming Chen,  Jing-Yang Jou
Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University

 

4:50PM
3B.4
Optimizing Simulated Annealing on GPU: A Case Study with IC Floorplanning
Yiding Han,  Sanghamitra Roy,  Koushik Chakraborty
Utah State University

 

5:10PM
3B.5
Floorplanning for high utilization of heterogeneous FPGAs
Nan Liu,  Song Chen,  Takeshi Yoshimura
Graduate School of Information,Production and Systems,Waseda University, Japan

 

 


 

SESSION 3C

Tuesday March 15 2011

 

Verification, Validation and Test

Chair: Sreejit Chakravarty
Co-Chair: Srivatsa Vasudevan

 

3:50PM
3C.1
Efficient Directed Test Generation for Validation of Multicore Architectures
Xiaoke Qin and Prabhat Mishra
University of Florida

 

4:10PM
3C.2
Global Transaction Ordering in Network-on-Chips for Post-Silicon Validation
Amir Masoud Gharehbaghi and Masahiro Fujita
University of Tokyo

 

4:30PM
3C.3
On Evaluating Signal Selection Algorithms for Post-Silicon Debug
Eddie Hung and Steven J. E. Wilton
University of British Columbia

 

4:50PM
3C.4
Debugging and Optimizing High Performance Superscalar Out-of-order Processors Using Formal Verification Techniques
Bijan Alizadeh1 and Masahiro Fujita2
1University of Tehran, 2University of Tokyo

 

5:10PM
3C.5
RF BIST for ADPLL-based Polar Transmitters with Wide-Band DCO Gain Calibration
Leyi Yin and Peng Li
Texas A&M University

 

 


 

SESSION

Tuesday March 15 2011

 

Poster Session & Mixer

Chair: Keith Bowman
Co-Chair: Kamesh Gadepally

 

5:30PM
P.1
A 90 nm Low-Power Successive Approximation Register For A/D Conversions
Mohamed Shaker and Magdy Bayoumi
University of Louisiana at Lafayette

 

5:30PM
P.2
A Low Noise CMOS Interface Circuit for Capacitive Liquid Crystal Chemical and Biological Sensor
Alireza Hassanzadeh1 and Robert G. Lindquist2
1PhD Student, ECE Dept. The University of Alabama in Huntsville, 2Professor,ECE Dept. The University of Alabama in Huntsville

 

5:30PM
P.3
Block-Basis On-Line BIST Architecture for Embedded SRAM Using Wordline and Bitcell Voltage Optimal Control
Masahiro Yoshikawa,  Shunsuke Okumura,  Yohei Nakata,  Yuki Kagiyama,  Hiroshi Kawaguchi,  Masahiko Yoshimoto
Kobe University

 

5:30PM
P.4
pH sensing with temperature compensation in a Molecular Biosensor for Drugs Detection
Daniela De Venuto1,  Sandro Carrara2,  Andrea Cavallini2,  Giovanni De Micheli2
1Politecnico di Bari, Italy, 2EPFL Switzerland

 

5:30PM
P.5
CMOS Diodes Operating Beyond Avalanche Frequency
Talal Al-Attar
Santa Clara University

 

5:30PM
P.6
Entropy-Reduced Hashing for Physical IP Management
Sandeep Koranne,  John Ferguson,  Bikram Garg,  Manish Khanna
Mentor Graphics

 

5:30PM
P.7
A Physical Model for Tunable Patch Antennas
Benjamin Horwath and Talal Al-Attar
Santa Clara University

 

5:30PM
P.8
Model Analysis of Multi-Finger MOSFET Layout in Ring Oscillator Design
Bo Jiang and Tian Xia
University of Vermont

 

5:30PM
P.9
Crosstalk Aware Coupled Line Delay Tree Construction for On-chip Interconnects
Tuhina Samanta1,  Sanoara Khatun1,  Hafizur Rahaman1,  Parthasarathi Dasgupta2
1Bengal Engineering and Science University, Shibpur, 2Indian Institute of Management, Calcutta, India

 

5:30PM
P.10
A Layer Prediction Method for Minimum Cost Three Dimensional Integrated Circuits
Tsu-Yun Hsueh,  Hsiang-Hui Yang,  Wei-Chieh Wu,  Mely Chen Chi
Department of Information and Computer Engineering, Chung Yuan Christian University

 

5:30PM
P.11
Delay Optimization Considering Power Saving in Dynamic CMOS Circuits
Kumar Yelamarthi1 and Henry Chen2
1Central Michigan University, 2Wright State University

 

5:30PM
P.12
Capacitor Free Phase Locked Loop Design in 45nm
Anisha Seli,  Hoa Nguyen,  Lili He,  Morris Jones
san jose state university

 

5:30PM
P.13
Model Based Double Patterning Lithography (DPL) and Simulated Annealing (SA)
Rance Rodrigues and Sandip Kundu
University of Massachusetts at Amherst

 

5:30PM
P.14
Comparative BTI Reliability Analysis of SRAM Cell Designs in Nano-Scale CMOS Technology
Shreyas Kumar Krishnappa and Hamid Mahmoodi
San Francisco State University

 

5:30PM
P.15
Design Method of NOR-Type Comparison Circuit in CAM with Ground Bounce Noise Considerations
Changmin Jung1,  Sanghyeon Baeg2,  ShiJie Wen3,  Richard Wong3
1LS Industrial Systems Co., Ltd., 2Hanyang Univeristy, 3Cisco Systems Inc.

 

5:30PM
P.16
Soft Error Hardened Redundant Pulsed Latch
Hossein Karimiyan Alidash1,  Sayed Masoud Sayedi2,  Vojin G. Oklobdzija3
1University of Kashan, 2Isfahan University of Technology, 3New Mexico State University

 

5:30PM
P.17
A 12-Bit CMOS Current Steering D/A Converter with a Fully Differential Voltage Output
Guoyuan Fu1,  H. Alan Mantooth1,  Jia Di2
1Electrical Engineering Department, University of Arkansas, Fayetteville, AR USA, 2Computer Science and Computer Engineering Department, University of Arkansas, AR USA

 

5:30PM
P.18
Fast Optimization of Nano-CMOS Mixed-Signal Circuits Through Accurate Metamodeling
Oleg Garitselov,  Saraju Mohanty,  Elias Kougianos
University of North Texas

 

5:30PM
P.19
CMP Monitoring and Prediction Based Metal Fill
Philippe Morey-Chaisemartin1,  Eric Beisser1,  Jean-Claude Marin2,  Lidwine Chaize2,  Julien Rosa2,  Pascal Guyader2
1Xyalis, 2STmicroelectronics

 

5:30PM
P.20
Non-Gaussian Uncertainty Propagation in Statistical Circuit Simulation
Qian Ying Tang and Costas Spanos
EECS, UC Berkeley

 

5:30PM
P.21
New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm
Randy Mann and Benton Calhoun
UVA

 

5:30PM
P.22
A Sensitivity-aware Methodology to Improve Cell Layouts for DFM Guidelines
Savithri Sundareswaran,  Robert Maziasz,  Mukhanov Konstantin,  Vladimir Rozenfeld,  Mikhail Sotnikov
Freescale Inc

 

5:30PM
P.23
Lithography-Aware Layout Modification Considering Performance Impact
Hongbo Zhang1,  Yuelin Du1,  Martin D. F. Wong1,  Kai-Yuan Chao2
1Dept. of ECE, UIUC, 2Intel Corporation

 

5:30PM
P.24
Tracking Hardware Evolution
Jose Augusto Nacif1,  Thiago Sousa Silva2,  Luiz Filipe Vieira2,  Alex Borges3,  Claudionor Jose Coelho Jr.2,  Antonio Otavio Fernandes2
1Universidade Federal de Viçosa, 2Universidade Federal de Minas Gerais, 3Universidade Federal de Juiz de Fora

 

5:30PM
P.25
An Accurate and Scalable MOSFET Aging Model for Circuit Simulation
Bogdan Tudor,  Joddy Wang,  Zhaoping Chen,  Robin Tan,  Weidong Liu,  Frank Lee
Synopsys, Inc.

 

5:30PM
P.26
Fast Variational Static IR-Drop Analysis on the Graphical Processing Unit
Rasit Topaloglu
GLOBALFOUNDRIES

 

5:30PM
P.27
Efficient Nanoscale VLSI Standard Cell Library Characterization Using a Novel Delay Model
Sandeep Miryala,  Baljit Kaur,  Bulusu Anand,  Sanjeev Manhas
IIT Roorkee

 

5:30PM
P.28
Occurrence Probability Analysis of a Path at the Architectural Level
Dheepakkumaran Jayaraman and Spyros Tragoudas
Southern Illinois University Carbondale

 

5:30PM
P.29
Automatic Post-layout Flow Validation Tool for Deep Sub-Micron Process Design Kits
pinping sun,  cole zemke,  wayne woods,  Nick Perez,  Hailing Wang,  Essam Mina,  Barbara DeWitt
IBM

 

5:30PM
P.30
Switching Constraint-driven Thermal and Reliability Analysis of Nanometer Designs
Srini Krishnamoorthy,  Vishak Venkatraman,  Yuri Apanovich,  Thomas Burd,  Anand Daga
Advanced Micro Devices

 

5:30PM
P.31
Separation of Communication and Computation in SystemC/TLM modeling: a Feature-Oriented Approach
Jun Ye,  Qingping Tan,  Tun Li
School of Computer Science, National University of Defense Technology

 

5:30PM
P.32
Integrated Scheduling, Allocation and Binding in High Level Synthesis using Multi Structure Genetic Algorithm based Design Space Exploration System
Anirban Sengupta and Reza Sedaghat
Ryerson University

 

5:30PM
P.33
Exploring Performance-Power Tradeoffs in Providing Reliability for NoC-Based MPSoCs
Hui Zhao,  Mahmut Kandemir,  Mary Jane Irwin
Penn State Univ

 

5:30PM
P.34
Stratus : Free design of highly parametrized VLSI modules interoperable with commercial tools
Sophie Belloeil-Dupuis,  Roselyne Chotin-Avot,  Habib Mehrez
UPMC/LIP6

 

 


 

SESSION 4A

Wednesday March 16, 2011

 

Variation, Reliability, and Test

Chair: Fedor Pikus
Co-Chair: Narendra Devta-Prasanna

 

10:20AM
4A.1
Variation-Aware Stochastic Extraction with Large Parameter Dimensionality: Review and Comparison of State of the Art Intrusive and Non-intrusive Techniques (Invited)
T. El-Moselhy and L. Daniel
Massachusetts Institute of Technology

 

10:40AM
4A.2
Digitally Programmable SRAM Timing for Nano-Scale Technologies
Adam Neale and Manoj Sachdev
University of Waterloo

 

11:00AM
4A.3
Layout-aware Mismatch Modeling for CMOS Current Sources with D/A Converter Analysis
Bo Liu,  Qing Dong,  Bo Yang,  Jing Li,  Shigetoshi Nakatake
University of Kitakyushu, Japan

 

11:20AM
4A.4
Using NMOS Transistors as Switches for Accuracy and Area-efficiency in Large-scale Addressable Test Array.
Weiwei Pan,  Jie Ren,  Yongjun Zheng,  Zheng Shi,  Xiaolang Yan
Zhejiang Univ.

 

11:40AM
4A.5
A Simple Array-Based Test Structure for the AC Variability Characterization of MOSFETs
Karthik Balakrishnan1,  Keith Jenkins2,  Duane Boning1
1Massachusetts Institute of Technology, 2IBM T.J. Watson Research Center

 

 


 

SESSION 4B

Wednesday March 16, 2011

 

Package and Processor Co-Design for Reliability and Signal/Power Integrity

Chair: Lalitha Immaneni
Co-Chair: Kamesh Gadepally

 

10:20AM
4B.1
Reliability - A Highly Important Product Attribute for the World's Poorest Consumers (Invited)
Joseph Fjelstad
Cheetah Gear

 

10:40AM
4B.2
Cost-effective Optimization of Serial Link System for Signal Integrity and Power Integrity
Raj Kumar Nagpal1,  Jai Narayan Tripathi2,  Rakesh Malik3
1Section Manager, 2Ph.D. Scholar, 3Group Manager

 

11:00AM
4B.3
Package-Chip Co-Design to Increase Flip-Chip C4 Reliability
Sheldon Logan and Matthew Guthaus
University of California, Santa Cruz

 

11:20AM
4B.4
Maximizing Hotspot Temperature: Wavelet based Modelling of Heating and Cooling Profile of Functional Workloads
Sudarshan Srinivasan,  Kunal P Ganeshpure,  Sandip Kundu
University of Massachusetts Amherst

 

 


 

SESSION 4C

Wednesday March 16, 2011

 

System Design Considerations

Chair: Rajesh Berigei
Co-Chair: Houman Homayoun

 

10:20AM
4C.1
Invited paper from SDM Committee (Session 4C)
TBA TBA
TBA

 

10:40AM
4C.2
Process Variation aware System-level Load Assignment for Total Energy minimization using Stochastic Ordering
Shahin Golshan,  Love Singhal,  Eli Bozorgzadeh
University of California, Irvine

 

11:00AM
4C.3
A Low Cost Approach to Calibrate On-Chip Thermal Sensors
Krishna Bharath,  Chunhua Yao,  Nam Sung Kim,  Parameswaran Ramanathan,  Kewal Saluja
University of Wisconsin-Madison

 

11:20AM
4C.4
Maximizing Throughput of Temperature-Constrained Multi-Core Systems with 3D-Stacked Cache Memory
Kyungsu Kang1,  Jongpil Jung1,  Sungjoo Yoo2,  Chong-Min Kyung1
1KAIST, 2POSTECH

 

 


 

SESSION 5A

Wednesday March 16, 2011

 

Error-Resilient Design

Chair: Riaz Naseer
Co-Chair: Srinivas Bodapati

 

1:30PM
5A.1
Design and Analysis of Metastable-Hardened and Soft-Error Tolerant High-Performance, Low-Power Flip-Flops
David Li,  David Rennie,  Pierce Chuang,  David Nairn,  Manoj Sachdev
University of Waterloo

 

1:50PM
5A.2
Enhanced Reliability Aware NoC Router
M. h Neishaburi and Zeljko Zilic
McGill University

 

2:10PM
5A.3
SEU Tolerant SRAM Cell
Sudipta Sarkar1,  Anubhav Adak1,  Virendra Singh1,  Kewal Saluja2,  Masahiro Fujita3
1Indian Institute of Science, 2Univ. of Wisconsin-Madison, 3Univ. of Tokyo

 

2:30PM
5A.4
Soft Error Reduction through Gate Input Dependent Weighted Sizing in Combinational Circuits
Warin Sootkaneung and Kewal K Saluja
Department of Electrical and Computer Engineering, University of Wisconsin-Madison

 

2:50PM
5A.5
Low Power Latch Design in Near Sub-Threshold Region to Improve Reliability for Soft Error
SANDEEP SRIRAM,  Haiqing Nan,  Ken Choi
Illinois Institute of Technology

 

3:10PM
5A.6
BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits
Mahesh Poolakkaparambil1,  Jimson Mathew2,  Abusaleh Jabir1,  Dhiraj Pradhan2,  Saraju Mohanty3
1Oxford Brookes University, 2University of Bristol, 3University of North Texas

 

 


 

SESSION 5B

Wednesday March 16, 2011

 

Routing, Signal Integrity, and Timing Closure

Chair: Martin Wong
Co-Chair: Vamsi Srikantam

 

1:30PM
5B.1
A Novel Fine-Grain Track Routing Approach for Routability and Crosstalk Optimization
Zhongdong Qi1,  Qiang Zhou1,  Yanming Jia1,  Yici Cai1,  Zhuoyuan Li2,  Hailong Yao1
1Tsinghua University, 2Magma Design Automation Inc.

 

1:50PM
5B.2
Redundant Via Insertion under Timing Constraint
Chi-Wen Pan and Yu-Min Lee
Institute of Communication Engineering, National Chiao-Tung University, Taiwan

 

2:10PM
5B.3
A New ECO Technology For Functional Changes and Removing Timing Violations
Jui-Hung Hung,  Yao-Kai Yeh,  Yung-Sheng Tseng,  Tsai-Ming Hsieh
Chung Yuan Christian University

 

2:30PM
5B.4
The Effect of SRNR on Timing Characteristics of Signal Busses
Bassel Soudan
University of Sharjah

 

2:50PM
5B.5
Gridless Wire Ordering, Sizing and Spacing with Critical Area Minimization
Yu-Wei Lee,  Yen-Hung Lin,  Yih-Lang Li
Department of Computer Science, National Chiao-Tung University

 

3:10PM
5B.6
Clock Planning for Multi-Voltage and Multi-Mode Designs
Chang-Cheng Tsai1,  Tzu-Hen Lin2,  Shin-Han Tsai1,  Hung-Ming Chen1
1NCTU, Taiwan, 2NTU, Taiwan

 

 


 

SESSION 5C

Wednesday March 16, 2011

 

Power Delivery and Estimation

Chair: Mark Budnik
Co-Chair: Syed Alam

 

1:30PM
5C.1
Fast Power Delivery Network Analyzer
Bosun Hwang,  Jongeun Koo,  Chanseok Hwang,  Younghoi Cheon,  Sooyoung Ahn,  Jongbae Lee,  Moonhyun Yoo
Samsung Electronics

 

1:50PM
5C.2
Efficient Checking of Power Delivery Integrity for Power Gating
Zhiyu Zeng1,  Zhuo Feng2,  Peng Li1
1Texas A&M University, 2Michigan Technological University

 

2:10PM
5C.3
An Efficient Statistical Chip-Level Total Power Estimation Method Considering Process Variations with Spatial Correlation
Zhigang Hao1,  Sheldon X.-D. Tan2,  Guoyong Shi1
1Shanghai Jiao Tong University, 2University of California, Riverside

 

2:30PM
5C.4
Statistical Full-Chip Dynamic Power Estimation Considering Spatial Correlations
Zhigang Hao1,  Ruijing Shen2,  Sheldon X.-D. Tan2,  Bao Liu3,  Guoyong Shi1,  Yici Cai4
1Shanghai Jiao Tong University, 2University of California, Riverside, 3University of Texas at San Antonio, 4Tsinghua University

 

2:50PM
5C.5
Stepped Supply Voltage Switching for Energy Constrained Systems
Sudhanshu Khanna,  Kyle Craig,  Yousef Shakhsheer,  Saad Arrabi,  John Lach,  Benton Calhoun
University of Virginia

 

3:10PM
5C.6
Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates
Kyungseok Kim and Vishwani Agrawal
Auburn University

 

 


 

SESSION 6A

Wednesday March 16, 2011

 

Design Methodologies for CMOS and Beyond

Chair: Saraju Mohanty
Co-Chair: Rasit Topaloglu

 

3:50PM
6A.1
Design of Ultra-low-leakage Logic Gates and Flip-flops in High-performance FinFET Technology (Invited)
Ajay Bhoj and Niraj Jha
Princeton University

 

4:10PM
6A.2
Timing Yield Estimation of Carbon Nanotube-based Digital Circuits in the Presence of Nanotube Density Variation and Metallic-Nanotubes
Behnam Ghavami,  Mohsen Raji,  Hossein Pedram
Amirkabir University of Technology

 

4:30PM
6A.3
Measuring Within-Die Spatial Variation Profile through Power Supply Current Measurements
Jim Plusquellic1,  Dhruva Acharyya2,  Kanak Agarwal3
1University of New Mexico, 2Verigy, 3IBM

 

4:50PM
6A.4
Analysis of Within-Die Process Variation in 65nm FPGAs
Tim Tuan,  Austin Lesea,  Chris Kingsley,  Steve Trimberger
Xilinx Inc.

 

5:10PM
6A.5
Estimating the Probability Density Function of Critical Path Delay via Partial Least Squares Dimension Reduction
Yu Ben and Costas Spanos
UC Berkeley

 

 


 

SESSION 6B

Wednesday March 16, 2011

 

Advanced Devices and Manufacturing Technologies

Chair: Paul Tong
Co-Chair: Bao Liu

 

3:50PM
6B.1
Complementary Nano-Electro-Mechanical Switch for Ultra-Low-Power Applications: Design and Modeling
Khawla Alzoubi1,  Daniel G. Saab2,  Massood Tabib-Azar3,  Sijing Han2
1Tafila Technical University, Jordan, 2Case Western Reserve, 3University of Utah

 

4:10PM
6B.2
Interconnection Aspects of Spin Torque Devices: Delay, Energy-Per-Bit, and Circuit Size Modeling
Shaloo Rakheja and Azad Naeemi
Georgia Institute of Technology

 

4:30PM
6B.3
Scaled LTPS TFTs for Low-Cost Low-Power Applications
Soo Youn Kim,  Selin Baytok,  Kaushik Roy
Purdue University

 

4:50PM
6B.4
Mitigating TSV-induced Substrate Noise in 3-D ICs using GND Plugs
Nauman Khan1,  Syed Alam2,  Soha Hassoun1
1Tufts University, 2Everspin Technologies Inc.

 

5:10PM
6B.5
Device and Circuit Implications of Double-Patterning - A Designer’s Perspective
Rasit Topaloglu
GLOBALFOUNDRIES

 

 


 

SESSION 6C

Wednesday March 16, 2011

 

New Ideas in Analog Design Automation

Chair: Masahiro Fujita
Co-Chair: Shireesh Verma

 

3:50PM
6C.1
Automatic Generation of Saturation Constraints and Performance Expressions for Geometric Programming based Analog Circuit Sizing
Supriyo Maji,  Samiran Dam,  Pradip Mandal
Indian Institute of Technology, Kharagpur

 

4:10PM
6C.2
Constructive AIG Optimization Considering Input Weights
Thiago Figueiró,  Renato Ribas,  André Reis
Universidade Federal do Rio Grande do Sul

 

4:30PM
6C.3
Integrated Hierarchical Synthesis of Analog/RF Circuits with Accurate Performance Mapping
Kuo-Hsuan Meng1,  Po-Cheng Pan2,  Hung-Ming Chen2
1UIUC, USA, 2NCTU, Taiwan

 

4:50PM
6C.4
A fully pipelined implementation of Monte Carlo based SSTA on FPGAs
Hiroshi Yuasa,  Hiroshi Tsutsui,  Hiroyuki Ochi,  Takashi Sato
Kyoto University

 

5:10PM
6C.5
Multi-mode Redundancy Removal
Stephen Plaza1,  Prashant Saxena2,  Thomas Shiple2,  Pei-Hsin Ho2
1Synopsys/HHMI, 2Synopsys

 

 


ISQED