ISQED 2026: Program (Rev. 0)

Wednesday April 8
                         Session 1A - Emerging transistors and circuits
Chair: TBA, TBA
10:15    Session 1A - 1A.1: Inter-Pixel Binary Edge-Detection (IPBED) Array
Md Rahatul Islam Udoy1, Md Mazharul Islam2, Garrett Rose1, Ahmedullah Aziz1
1University of Tennessee, Knoxville, 2The University of Tennessee
10:35    Session 1A - 1A.2: Fault Tolerant Design of IGZO-based Binary Search ADCs
Paula Carolina Lozano Duarte1, Sule Ozev2, Mehdi Tahoori1
1Karlsruhe Institute of Technology, 2ASU
10:55    Session 1A - 1A.3: Thermal-Aware Compact Modeling and Design-Space Exploration of δ-Doped β-Ga2O3 MOSFETs for RF Power Electronics
Habibullah Khan, Nabasindhu Das, Nidhin Kurian Kalarickal, Kexin Li
Arizona State University
11:15    Session 1A - 1A.4: Temperature-Dependent Current–Voltage Model for Emerging GAA NS FETs Using a Physics-Inspired Neural Network
Yiming Li, Yun Tai, Min-Hui Chuang
National Yang Ming Chiao Tung University
11:35    Session 1A - 1A.5: Pioneering the Use of Response Surface Modeling for Complementary Field-Effect Transistors Design and Optimization
Yu-Wen Xu and Yiming Li
National Yang Ming Chiao Tung University
Wednesday April 8
                         Session 1B - Foundations of Cryptographic Hardware Security
Chair: TBA, TBA
10:15    Session 1B - 1B.1: OK-BMM: A Power-Performance-Efficient Overlap-Free Karatsuba Based Barrett Modular Multiplier for Secure Embedded Systems
Bhavana S1, Keerthana B2, Madhav Rao3
1International Institute of Information Technology, Bangalore, 2International Institute of Information Technology Bangalore, 3International Institute of Information Technology-Bangalore
10:35    Session 1B - 1B.2: R-BMM: A Reconfigurable Barrett Modular Multiplier Architecture for High-Performance Cryptographic Systems
Keerthana B1, Bhavana S2, Madhav Rao3
1International Institute of Information Technology Bangalore, 2International Institute of Information Technology, Bangalore, 3International Institute of Information Technology-Bangalore
10:55    Session 1B - 1B.3: A Low-overhead Dilithium-NTT Architecture using Accelerated K-RED Modular Reduction Unit
Harsh Gupta1, Aryan Goyal1, Paranjay Dhadwal1, Jugal Gandhi2, Diksha Shekhawat3, Jai Gopal Pandey4
1Birla Institute of Technology and Science (BITS) Pilani Goa Campus, 2AcSIR at CSIR-CEERI, 3AcSIR, CSIR-CEERI, 4CSIR -Central Electronics Engineering Research Institute (CEERI), Pilani, Rajasthan, India
11:15    Session 1B - 1B.4: STREAMLOCK: Stream Cipher-Enabled Cryptographic Logic Locking
Nahush D Tambe1, DHRUVAKUMAR AKLEKAR2, Naseeruddin Lodge2, Vineet Chadalavada3, fareena saqib2
1University f North Carolina at Charlotte, 2UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE, 3UNC Charlotte
11:35    Session 1B - 1B.5: Hardware-Efficient Compound IC Protection with Lightweight Cryptography
Levent Aksoy1, Muhammad Sohaib Munir1, Sedat Akleylek2
1Tallinn University of Technology, 2University of Tartu
Wednesday April 8
                         Session 1C - From Specifications to Silicon: Advanced Verification Across the Hardware Stack
Chair: Chidhambaranathan Rajamanikkam, Synopsys
Co-Chair: Sushant Sadangi, Intel
10:15    Session 1C - 1C.1: Specification-Driven INL Generation for Behavioral ADC Models with Controlled Error Injection
Thorben Schey1, Khaled Karoonlatifi2, Michael Weyrich1, Andrey Morozov1
1University of Stuttgart, 2Advantest Europe GmbH
10:35    Session 1C - 1C.2: Verifying Hardware Resource Isolation Using Mandatory Access Control
Christopher R Nokes1, Kostas Amberiadis2, D. Richard Kuhn3, Edwards E Reed4, Michael Zuzak1
1Rochester Institute of Technology, 2National Institute of Standards and Technology, 3Virginia Tech, 4AESEC Global Services, Inc.
10:55    Session 1C - 1C.3: Scalable Hardware–Software Co-Verification through Linux Driver Reuse: Methodology Validated on USB4 and xHCI Host Controllers.
Suchir Gupta, Amit Sharma, Suneetha Suryadevara, Vishnuvardhan reddy mandala
Synopsys
11:15    Session 1C - 1C.4: Cutwidth Decomposition on Circuit-AIGs: Taming Verification Complexity of Arithmetic Circuits
Luca Müller1, Mohamed Nadeem2, Rolf Drechsler1
1University of Bremen/DFKI, 2University of Bremen
Wednesday April 8
                         Session 2A - AI and Machine Learning in Hardware Design
Chair: TBD, TBD
Co-Chair: TBD, TBD
13:40    Session 2A - 2A.1: BPINN-EM-Post: Bayesian Physics-Informed Neural Network based Stochastic Electromigration Damage Analysis in the Post-void Phase
Subed Lamichhane1, Haotian Lu1, Sheldon Tan2
1University of California, Riverside, 2University of California at Riverside
14:00    Session 2A - 2A.2: AutoBeaVer: Automating Behavioral Modeling and Verification in Library Characterization with LLM Agents
Tianze Wu1, Jian Xin2, Yuan Wang2, Xuliang Yu1, Xunzhao Yin1, Qianqian Yang1, Zuochang Ye2, Liang Zhao1
1Zhejiang University, 2Tsinghua University
14:20    Session 2A - 2A.3: An AI-Enhanced STA Framework Supporting CCS and SI with Signoff Accuracy
Chao Yan
Hexin
14:40    Session 2A - 2A.4: Integrating Automatic Prompt Engineering and Vision-Language Model for Pad Defect Classification
Yi-Ting Shen1, Yan-Hsiu Liu2, Yi-Ting Li1, Wuqian Tang1, Yung-Chih Chen3, Hao-Chiang Shao4, Chia-Wen Lin1, Chun-Yao Wang1
1National Tsing Hua University, 2United Microelectronics Corporation, 3National Taiwan University of Science and Technology, 4National Chung Hsing University
15:00    Session 2A - 2A.5: Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
Yuchao Liao, Tosiron Adegbija, Roman Lysecky
University of Arizona
Wednesday April 8
                         Session 2B - Detection, Validation, and Reverse Engineering of Malicious Hardware
Chair: Hassan Salmani, TBA
13:40    Session 2B - 2B.1: Reference-Free EM Validation Flow for Detecting Triggered Hardware Trojans
Mahsa Tahghigh and Hassan Salmani
Howard University
14:00    Session 2B - 2B.2: Reliable Hardware Trojan Detection for RISC-V Processors using Formal Verification and Automation
Czea Sie Chuah1, Christian Appold2, Tim Leinmüller2
1Technical University of Munich, 2DENSO AUTOMOTIVE Deutschland GmbH
14:20    Session 2B - 2B.3: BERT-HIT: A Transformer-Based Approach for Hardware Trojan Detection in Gate-Level Netlists
Lizi Zhang1, Navid Nader Tehrani1, Azadeh Davoodi2, Rasit Onur Topaloglu3
1University of Wisconsin, Madison, 2University of Wisconsin - Madison, 3Adeia
14:40    Session 2B - 2B.4: Reverse Engineering RTL Models from DSP Slices in FPGA Netlists
Avinash Hegde Kota1, Aparajithan Nathamuni-Venkatesan2, Ranga Vemuri3, John Martin Emmert2
1Digital Design Environments Lab, Dept. of ECE, University of Cincinnati, 2University of Cincinnati, 3Univ of Cincinnati
15:00    Session 2B - 2B.5: Security-Aware Printed-Circuit-Board Routing Based on Deep Reinforcement Learning
Katherine Shu-Min Li1, Ching-Han Lai1, Fang-Chi Wu1, Sying-Jyan Wang2
1National Sun Yat-sen University, 2National Chung Hsing University
Wednesday April 8
                         Session 2C - AI & Machine Learning Acceleration – Architectures and Co-Design
Chair: TBA, TBA
13:40    Session 2C - 2C.1: Carbon Emission-Based Sustainability Model For Photonic Neural Network Accelerators
Siqin Liu1, Avinash Karanth1, Ahmed Louri2
1Ohio University, 2George Washington University
14:00    Session 2C - 2C.2: FlexGO: A Unified Overlay for General Graph Neural Network Acceleration
Pramath Balisavira, Rishov Sarkar, Cong Hao
Georgia Institute of Technology
14:20    Session 2C - 2C.3: Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multi-lingual Neural Machine Translation
Mukul Lokhande1, Tanushree Dewangan1, Sharik Mansoori2, Tejas Chaudhari3, Akarsh J.1, Damayanti Lokhande4, Adam Teman5, Santosh Vishvakarma6
1Indian Institute of Technology Indore, 2Undergraduate, 3Indian Institute of Technology, Indore, 4Independent, 5Bar-Ilan University, 6IIT Indore
14:40    Session 2C - 2C.4: TinyQL: A Quantum Machine Learning Framework at Edge for Resource-Constrained IoT Devices
Maurice Ngouen, Mohammad Ashiqur Rahman, Alexander Perez-Pons, Nagarajan Prabakar
Florida International University
15:00    Session 2C - 2C.5: Hardware Software Co-Optimization for RISC-V Based High-Performance Hyperdimensional Computing Architectures
Priyanka Agarwal1, Arun M2, Chandan KUMAR N S3, Shrinidhi Soorinje Rao2, Madhav Rao2
1IIIT Bangalore, 2International Institute of Information Technology-Bangalore, 3International Institute of Information Technology Bangalore
Thursday April 9
                         Session PW1 - Short Presentation & WIP Session 1
Chair: TBA, TBA
9:40    Session PW1 - PW1.1: Sparsity Aware Pre-processing for Systolic Array Dataflow Acceleration
Tadikonda Venkata Sai Chaitanya1, Bhargav D V2, Madhav Rao2
1International Insititute of Information Technology-Bangalore, 2International Institute of Information Technology-Bangalore
9:45    Session PW1 - PW1.2: Cascaded Reservoir Computing for Temporal Sensor Data: Integrating Physical Dynamics with Echo State Networks
Md Razuan Hossain1, Imran Fahad2, Braylen Robinson2, Sai Swaminathan2, Hritom Das3
1Utah Valley University, 2The University of Tennessee, Knoxville, 3Oklahoma State University
9:50    Session PW1 - PW1.3: NeuroMap: A Scalable Toolchain for Mapping Memristor-based Spiking Neural Networks
Zhewei Wang, Ye Yue, Mansour Rezaei, Caleb Mcalpine, Ismail Tirtom, Savas Kaya, Avinash Karanth
Ohio University
9:55    Session PW1 - PW1.4: VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
Haomin Qi1, Yuyang Du2, Lihao Zhang2, Soung Chang Liew2, Kexin Chen2, Yining Du2
18582149887, 2The Chinese University of Hong Kong
10:00    Session PW1 - PW1.5: Semantic-Guided Test Generation using Fine-Tuned LLMs for Validation of Hardware Accelerators
Emma Andrews1, Aruna Jayasena2, Prabhat Mishra1
1University of Florida, 2University of Tennessee
10:05    Session PW1 - PW1.6: TCAD-Based GGNMOS Digital-Twin for ESD Characterization & Sensitivity Analysis
Kunaal Pulli1, Mehrdad Nourani2, Charvaka Duvvury3
1University of Texas at Dallas, 2The University of Texas at Dallas, 3iT2 Technologies
10:10    Session PW1 - PW1.7: HDL-DFGen: A Digital Filter Hardware Description Generation Framework
Pedro Pereira1, Sergio Bampi2, Eduardo Costa2
1Universidade Federal do Rio Grande do Sul, 2UFRGS - Federal Univ. of Rio Grande do Sul
10:15    Session PW1 - PW1.8: Automatic Compact Model Parameter Extraction with an Enhanced Hybrid of Differential Evolution and Nelder-Mead Optimizers
Fahad Ali Usmani, Zijian Song, Roberto Tinti
Engineer
10:20    Session PW1 - PW1.9: AutoSim: A Declarative Framework for Simulator-Agnostic Hardware Verification Automation
Bhagirath K, Dheeraj Pant, Abhishek Tiwari, Vivek Khaneja
Centre for Development of Advanced Computing
Thursday April 9
                         Session PW2 - Short Presentation & WIP Session 2
Chair: TBA, TBA
9:40    Session PW2 - PW2.1: FSMVision: Semantic Extraction of Finite State Machines from Diagrams via Multimodal AI
Sagor Chandro Bakchy1, Muhammad Aminul Islam2, Sazadur Rahman3, Md Tauhidur Rahman1
1Florida International University, 2University of New Haven, 3University of Central Florida
9:45    Session PW2 - PW2.2: Multi-Die Concurrent Global Placement with Macro Flipping-aware Wirelength Modelfor 3D-ICs
Anh Minh Phan1, Cheng-Xun Song1, Sheng-Tan Huang2, Shao-Yun Fang1, Tung-Chieh Chen3, Kai-Shun Hu3, Chin-Fang Cindy Shen3
1National Taiwan University Of Science and Technology, 2m11207418@mail.ntust.edu.tw, 3Synopsys Taiwan Co., Ltd.,
Download File
9:50    Session PW2 - PW2.3: Modeling Endurance Degradation of VCM-based 1T1R ReRAM Cell for Circuit Simulations
Supriya Chakraborty1, Seyed Hossein Hashemi Shadmehri2, Thiago Santos Copetti2, Tobias Gemmeke2, Leticia Maria Bolzani Poehls3
1RWTH Aachen University, 2RWTH Aachen University, 3IHP - Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Germany
9:55    Session PW2 - PW2.4: Monolithic 3D Integration for Null Convention Logic (NCL)-Based Asynchronous Circuits
Xiameng Zhang1, Ashiq A Sakib2, Kushal K. Ponugoti3, Madhava Sarma Vemuri1
1University of Washington Bothell, 2Southern Illinois University Edwardsville, 3North Dakota State University
10:00    Session PW2 - PW2.5: Data Augmentation Strategies for Machine Learning-based Compact Modeling of Emerging Devices
Diego Ferrer1, Md Mazharul Islam2, Wei Pan3, Juan Pedro Mendez Granado3, Denis Mamaluy3, Ahmedullah Aziz4
1The University of Tennessee, Knoxville, 2The University of Tennessee, 3Sandia National Laboratory, 4University of Tennessee, Knoxville
10:05    Session PW2 - PW2.6: A Compact Gray-Code Quantum Read-only Memory for the NISQ Era
Hao Yu Lu1, Yu-Ting Kao2, Yeong-Jar Chang2, Chao-Hung Wang1, Darsen Lu1
1National Cheng Kung University, 2Industrial Technology Research Institute
10:10    Session PW2 - PW2.7: Trusted Memory Access Monitoring (TMAM): Detecting Fine-Grained DDR4 Access Patterns in FPGA Clouds
Vineet Chadalavada1, Nahush Tambe1, Naseeruddin Lodge1, Dhurva Aklekar1, fareena saqib2
1UNC Charlotte, 2University of North Carolina at Charlotte
10:15    Session PW2 - PW2.8: Unsupervised Learning Based Hardware Trojan Detection Method for RTL Designs
Sying-Jyan Wang and Hou-Cheng Chen
National Chung Hsing University
10:20    Session PW2 - PW2.9: Reusing Assertion Properties as Hardware Checkers: Implementation and their Software and Hardware Recovery
Czea Sie Chuah1, Christian Appold2, Tim Leinmueller2
1Technical University of Munich, 2DENSO AUTOMOTIVE Deutschland GmbH
Thursday April 9
                         Session PW3 - Short Presentation & WIP Session 3
Chair: TBA, TBA
9:40    Session PW3 - PW3.1: Detecting Hardware Trojans in Quantum Circuits Based on CodeBERT model
Min-Chao Huang1, Chin-Wei Tien2, Sy-Yen Kuo1
1National Taiwan University, 2Trend Micro
9:45    Session PW3 - PW3.2: Unsupervised Detection of Ring-Oscillator Hardware Trojans via Autoencoder Power Analysis
Oyshi Sarker1 and Jaya Dofe2
1California State University Fullerton, 2California State University
Download File
9:50    Session PW3 - PW3.3: Characterizing On-Chip Variability of Anderson PUFs Across Multiple FPGAs
Quoc Huy Lieu1 and Jaya Dofe2
1California State University Fullerton, 2California State University
Download File
9:55    Session PW3 - PW3.4: TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs
Shuyang Li1, Hanqing Zhang2, Ruiqi Chen3, Bruno da Silva3, Giorgian Borca-Tasciuc4, Dantong Yu5, Cong Hao1
1Georgia Institute of Technology, 2Zhejiang University, 3Vrije Universiteit Brussel, 4Rensselaer Polytechnic Institute, 5New Jersey Institute of Technology
10:00    Session PW3 - PW3.5: Enhanced Hybrid Temporal Computing Using Deterministic Summations for Ultra-Low-Power Accelerators
Sachin Sachdeva1, Jincong Lu1, Wantong Li1, Sheldon Tan2
1University of California, Riverside, 2University of California at Riverside
10:05    Session PW3 - PW3.6: POSEIDON: A Posit-Optimized Out-of-Order Processor with Transformer Acceleration for Edge Devices
Niranjan Gopal1, Madhav Rao2, Harshvardhan Mishra3, Gaurav Ravindra Nayak4
1International Institute of Information Technology Bangalore, 2International Institute of Information Technology-Bangalore, 3IIIT-B, 4IIITB
10:10    Session PW3 - PW3.7: Real-Time Edge Semantics for Drone Swarms via FPGA Perception and On-Device LLMs
Zhaoqi Wang, Wade Alexander Fortney, Gabriel Bendix, Yu Feng, Christophe Bobda
University of Florida
10:15    Session PW3 - PW3.8: RACFlow: An Evolutionary Framework for Compact Reconfigurable Approximate Circuits
Bhargav D V and Madhav Rao
International Institute of Information Technology-Bangalore
10:20    Session PW3 - PW3.9: Active Interposers for High Bandwidth Memory
Andres Ayes and Eby Friedman
University of Rochester
Thursday April 9
                         Session 3A - Advanced Circuit Modeling and Analysis
Chair: TBD, TBD
Co-Chair: TBD, TBD
10:45    Session 3A - 3A.1: Effective Capacitance Modeling Using Graph Neural Networks
Eren Dogan1 and Matthew Guthaus2
1University of California, Santa Cruz, 2UC Santa Cruz
11:05    Session 3A - 3A.2: Gate-Level Average Power Estimation from RTL Activity with Graph Neural Network
Ssu-Chen Chang1, Yung-Chih Chen2, Chun-Yao Wang3, Jian-Meng Yang4, Pei-Ying Liu5
1National Taiwan University of Science and Technology, 2National Taiwan University of Science and Technology; Arculus System Co. Ltd., 3Dept. CS, National Tsing Hua University, 4Arculus System, 5MicroIP
11:25    Session 3A - 3A.3: Multi-Node Timing and Power Estimation with Adapter-Based Transfer Learning
Luis Humberto Pena Trevino1, Eric Guerra Ribeiro2, Lirida Naviner1, Fady Abouzeid2, Philippe Roche2
1Télécom Paris, 2STMicroelectronics
11:45    Session 3A - 3A.4: Efficient High-Sigma Yield Analysis based on Deep Ensemble Framework with Active learing and Augmentation
Younghun Park1, KIM KANG HUN2, Jun Seo Jung1, Juho Kim1
1Sogang University, 2Sogang Univ
12:05    Session 3A - 3A.5: Parasitics-Aware Framework for Integrated OTA Sizing and Layout Synthesis in FinFET Technologies
Endalk Y Gebru, Subhadip Ghosh, Ramesh Harjani, Sachin S. Sapatnekar
University of Minnesota
Thursday April 9
                         Session 3B - NN Acceleration & Dataflow Optimization
Chair: TBA, TBA
10:45    Session 3B - 3B.1: Accelerating Machine Learning Applications through Optimized Tensor Decompositions
Emma Andrews and Prabhat Mishra
University of Florida
11:05    Session 3B - 3B.2: Harmony: A Hardware-Mapping Co-Exploration Framework for Hybrid CIM-based Vision Transformer Accelerator
Yihang Zuo1, Zexin Fu2, Cong Wang3, Yuchao Wu4, Jiayi Huang2, Yuzhe Ma2
1Arizona State University, 2The Hong Kong University of Science and Technology (Guangzhou), 3The Hong Kong University of Science and Technology(Guangzhou), 4The Hong Kong University of Science and Technology
11:25    Session 3B - 3B.3: BiKA: Kolmogorov-Arnold-Network-inspired Ultra Lightweight Neural Network Hardware Accelerator
Yuhao Liu1, Salim Ullah2, Akash Kumar3
1Technische Universitaet Dresden, 2Ruhr-Universität Bochum, 3Ruhr University Bochum
11:45    Session 3B - 3B.4: Cross-Layer Co-Optimized LSTM Accelerator for Real-Time Gait Analysis
Mohammad Hasan Ahmadilivani1, Levent Aksoy2, Mohammad Eslami3, Alar Kuusik2, Jaan Raik2
1Tallinn University of Tehnology, 2Tallinn University of Technology, 3Department of Computer Systems, Tallinn University of Technology
12:05    Session 3B - 3B.5: Mixed-Precision Booth Factored Systolic Array Design for Accelerating Neural Networks
Sneha Dandekar1, Bhavana S2, Madhav Rao3
1International Institute of Information Technology - Bangalore, 2International Institute of Information Technology, Bangalore, 3International Institute of Information Technology-Bangalore
Thursday April 9
                         Session 3C - Security for AI and AI for Security
Chair: TBA, TBA
Thursday April 9
                         Session 4A - Innovative Design Methodologies and Frameworks
Chair: TBD, TBD
Co-Chair: TBD, TBD
14:10    Session 4A - 4A.1: A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
Aybars Yunusoglu1, Talha Coskun2, Hiruna Vishwamith3, Murat Isik4, I. Can Dikmen5
1Purdue University, 2University of Illinois Urbana-Champaign, 3University of Moratuwa, 4Stanford University, 5Istinye University
14:30    Session 4A - 4A.2: Design for Manufacturing and Assembly for Heterogeneous Integration using Micro-Transfer Printing
Robert Fischbach1, Ronny Frevert2, Andreas Krinke1, Sebastian Wicht3, Jens Lienig1
1Dresden University of Technology, 2X-FAB Dresden GmbH & Co. KG, 3X-FAB Semiconductor Foundries
14:50    Session 4A - 4A.3: GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
Dimple Vijay Kochar1, Nathaniel Pinckney2, Guan-Ting Danny Liu3, Chia-tung Ho4, Chenhui Deng4, Haoxing Ren2, Brucek Khailany4
1Massachusetts Institute of Technology, 2NVIDIA Corporation, 3NVIDIA Research, 4Nvidia
15:10    Session 4A - 4A.4: Thor: Towards General Directed Circuit Graph Encoder with Sample-Efficient Graph Contrastive Learning
Wencheng Zou1, Yiran Xia2, Haoyu Wang3, Pan Li3, Nan Wu1
1George Washington University, 2Hong Kong University of Science and Technology, 3Georgia Institute of Technology
15:30    Session 4A - 4A.5: Area-Oriented Threshold Logic Circuit Synthesis Using Negative Weights
Yu-Chuan Yen1, Fu-Cheng Cai1, Yi-Ting Li1, Wuqian Tang1, Yung-Chih Chen2, Ihao Chen3, Chun-Yao Wang1
1National Tsing Hua University, 2National Taiwan University of Science and Technology, 3Incentia Design Systems Inc.
Thursday April 9
                         Session 4B - Fault, Memory, and Physical Attacks on Hardware Systems
Chair: TBA, TBA
14:10    Session 4B - 4B.1: Descrambling the Scrambler: Experimental Extraction of Data Scrambling Keys in COTS NAND Flash
Matchima Buddhanoy1, Habib Ur Rahman1, Aleksandar Milenkovic2, Sudeep Pasricha1, Biswajit Ray1
1Colorado State University, 2The University of Alabama in Huntsville
14:30    Session 4B - 4B.2: Characterization of the Stability of DRAM Read Disturbances
Roberto Capoferri1, Alessandro Barenghi2, Luca Oddone Breveglieri1, Khalil Gammoh3, Niccolò Izzo3, Gerardo Pelosi1
1Politecnico di Milano, 2Politecnico di Milano - DEIB, 3Micron
14:50    Session 4B - 4B.3: Power-Off Laser Attack Against Bulk Built-in Current Sensors
Raphael C Viera, Noé Backert, Jean-Max Dutertre
Mines Saint-Etienne
15:10    Session 4B - 4B.4: An Efficient Memory Cell Flipping Technique Under Covert Channel Attacks
Prokash Ghosh1, Sundeep Agrawal1, Sonali Sunil Dulange1, Subhajit Dutta Chowdhury2
1AMD Inc, USA, 2AMD
15:30    Session 4B - 4B.5: CRISP: Platform-Agnostic Unified Reconfigurable Hardware Security Primitive
Atri Chatterjee, Sudipta Paria, Aritra Dasgupta, Habibur Rahaman, Baibhab Chatterjee, SWARUP BHUNIA
University of Florida
Thursday April 9
                         Session 4C - Neuromorphic Computing
Chair: TBA, TBA
Friday April 10
                         Session 5A - Quantum and memory technology and circuits
Chair: TBA, TBA
8:40    Session 5A - 5A.1: Delay Register Minimization in RSFQ Circuits
Chi-En Hsu and Wai-Kei Mak
Department of Computer Science, National Tsing Hua University
9:00    Session 5A - 5A.2: The Art of Optimizing T-Depth for Quantum Error Correction in Large-Scale Quantum Computing
Avimita Chatterjee1, Archisman Ghosh2, Swaroop Ghosh1
1Pennsylvania State University, 2The Pennsylvania State University
9:20    Session 5A - 5A.3: ULTRARAM: An Emerging Memory Platform for NVM and Low-Power Neuromorphic Systems
Abhishek Kumar1, Musaibh Farooq Dar2, Peter D. Hodgson3, Dominic Lane3, Peter J. Carrington3, Evangelia Delli3, Richard Beanland4, Shruti Mehrotra5, James Ashforth-Pook6, Manus Hayne3, Avirup Dasgupta2
1University of California Berkeley, 2Indian Institute of Technology Roorkee, 3Lancaster University, 4Warwick University, 5GlobalFoundries, 6QuInAs Technology Limited
9:40    Session 5A - 5A.4: RRAM Crossbar Design with AC Driving for Parallel Computing-In-Memory
Guanyu Chi1, Ing-Chao Lin2, Ulf Schlichtmann1
1Technical University of Munich, 2National Yang Ming Chiao Tung University
10:00    Session 5A - 5A.5: Design and Simulation of Long-Retention Capacitorless 1T-DRAM Using Experimentally Calibrated Process and Device Simulations
Shao-Han Cheng1, Chun-Hung Wang1, Fu-Chang Hsu2, Yao-Jen Lee3, Yiming Li3
1National Yang Minlg Chiao Tung University, 2NEO Semiconductor Inc., 3National Yang Ming Chiao Tung University
Friday April 10
                         Session 5B - Memory Systems, Approximate Computing, and System-Level Optimization
Chair: TBA, TBA
8:40    Session 5B - 5B.1: Multi-Level Cell Memory Driven Efficient Cache Organization
Binu Christopher1, Rwicheek Sarker1, Vivek M Bhasi2, Sumitha George1
1North Dakota State University, 2The Pennsylvania State University
9:00    Session 5B - 5B.2: PEARL: Page Migration for Efficient Hybrid Memory Systems using Adaptive and Lightweight Reinforcement Learning
Jash Vipul Ratanghayra, Aswathy N S, Hemangee Kapoor
Indian Institute of Technology Guwahati
9:20    Session 5B - 5B.3: Bit-Flexible Systolic Architecture: Optimizing Processing Elements with Application-Specific Floating-Point Truncation
Dantu Nandini Devi1 and Madhav Rao2
1International Institute of Information Technology Bangalore, 2International Institute of Information Technology-Bangalore
9:40    Session 5B - 5B.4: VAE-Enabled Design Space Exploration for Heterogeneous Approximate Matrix Multiplication Accelerators
Niranjan Gopal1, Nishith Akula2, Madhav Rao3
1International Institute of Information Technology Bangalore, 2International Institute of Information Technology, Bangalore, 3International Institute of Information Technology-Bangalore
10:00    Session 5B - 5B.5: Crossing the Layers and Dotting the Details: Systematic Exploration of Near-Memory Computing
Riselda Kodra1, Rafael Medina Morillas2, Marina Zapater3, Giovanni Ansaloni1, David Atienza4
1EPFL, 2ETH Zurich, 3University of Applied Sciences Western Switzerland (HES-SO), 4École Polytechnique Fédérale de Lausanne (EPFL)
Friday April 10
                         Session 5C - Neuromorphic and Approximate Computing Hardware for Next-Generation AI
Chair: Harsh Patel, Microsoft Inc
8:40    Session 5C - 5C.1: BM-HPR Mul: Error Tolerant Hardware Efficient Booth Modified High Precision Redundant Multiplier
Chandan KUMAR N S1, Yerasi Manoj Reddy1, Madhav Rao2
1International Institute of Information Technology Bangalore, 2International Institute of Information Technology-Bangalore
9:00    Session 5C - 5C.2: A Low-Power Analog Spiking Neural Network with On-Chip Learning
Kiruthikan Sithamparanathan and Jeffery Dix
University of Arkansas
9:20    Session 5C - 5C.3: Hardware-Efficient and Precision-Aware FP16 Approximate Multipliers: A Probabilistic Approach
Bindu G Gowda1 and Madhav Rao2
1International Institute of Information Technology, Bangalore, 2International Institute of Information Technology-Bangalore
9:40    Session 5C - 5C.4: A 4 Transistor eDRAM-Based Content Addressable Memory
Kayode Oluwaseyi Adebunmi1 and Akhilesh Jaiswal2
1University of Wisconsin Madison, 2University of Wisconsin-Madison
Friday April 10
                         Session 6A - Timing and Placement Optimization Techniques
Chair: TBD, TBD
Co-Chair: TBD, TBD
10:30    Session 6A - 6A.1: Timing-Aware Placement Algorithm for Rapid Single-Flux-Quantum Circuits
Zhaoting Zhang, Pengming Chen, Zepeng Li, Genggeng Liu
Fuzhou University
10:50    Session 6A - 6A.2: Hybrid GCN-CNN Framework for Fast Timing-driven Layer Assignment in Global Routing
Sai Harika Julakanti and Vidya A. Chhabria
Arizona State University
11:10    Session 6A - 6A.3: Cost-Effective Co-Optimization of SoC Partitioning and Chiplet-Level Global Placement for 2.5D Integration
Chou-Yen-Chih Li1, Chih-Yu Li1, Yung-Chih Chen2, Liang-Chia Cheng3
1National Taiwan University of Science and Technology, 2National Taiwan University of Science and Technology; Arculus System Co. Ltd., 3Industrial Technology Research Institute
11:30    Session 6A - 6A.4: Advanced Techniques for NP3-Boolean Matching: Leveraging Multi-bit Ports and Reverse Engineering to Minimize Search Space
Kai-Po Hsu1, Yi-Ting Li1, Fu-Cheng Cai2, Chia-Feng Chien1, Wuqian Tang2, Ting-Yu Ku1, Yu-Chen Cheng1, Tsung-Han Lai1, Cheng-Lung Wang1, Yi-Ting Shen1, Kuan-Ling Chou1, Zi-Wei Huang1, Tao-Chun Huang1, Tzu-Li Hsu1, Yung-Chih Chen3, Shih-Chieh Chang1, Ting-Chi Wang1, TingTing Hwang1, Chun-Yao Wang1
1National Tsing Hua University, 2National Tsing Hua Univer, 3National Taiwan University of Science and Technology
11:50    Session 6A - 6A.5: VHDLBench — a Dataset with Rich Contextual Relationships for Training Custom LLMs
Arpit Sakhreliya and Manoj Franklin
University of Maryland, College park
Friday April 10
                         Session 6B - Security and Robustness of Machine Learning Hardware
Chair: Amin Rezaei, TBA
10:30    Session 6B - 6B.1: Tiny Changes, Big Drops: Unveiling Security Vulnerabilities in ML Accelerators
Filip Grimsholm1, Cassandra Westergren1, Mahdi Fazeli1, Ahmad Patooghy2
1Halmstad University, 2North Carolina A&T State University
10:50    Session 6B - 6B.2: GBFA: Gradual Bit-Flip Fault Attack on Graph Neural Network Accelerators
Sanaz Kazemi and Sai Manoj Pudukotai Dinakarrao
George Mason University
11:10    Session 6B - 6B.3: Ralts: Robust Aggregation for Enhancing Graph Neural Network Resilience on Bit-flip Errors
Wencheng Zou and Nan Wu
George Washington University
11:30    Session 6B - 6B.4: A Data-Free Membership Inference Attack on Federated Learning in Hardware Assurance
Gijung Lee1, Wavid Bowman1, Olivia P. Dizon-Paradis1, Reiner N. Dizon-Paradis1, Ronald Wilson2, Damon Woodard2, Domenic Forte2
1Florida Institute for National Security, University of Florida, 2University of Florida
11:50    Session 6B - 6B.5: Confidential and Efficient Implementation of Lightweight Large Language Models
Hui Feng, Ben Dong, Qian Wang
University of California, Merced
Friday April 10
                         Session 6C - Emerging AI workloads on NPUs
Chair: TBA, TBA
Friday April 10
                         Session 7A - Hyperdimensional, Neuromorphic, and Robust Cognitive Computing Hardware
Chair: TBA, TBA
12:55    Session 7A - 7A.1: A Mixed-Signal Neuromorphic Accelerator for Energy Efficient Inference in Event-Based Neural Network Models
Armin Abdollahi1, Mehdi Kamal1, Massoud Pedram2
1University of Southern California, 2USC
13:15    Session 7A - 7A.2: Training Once, Deploy Anywhere: Defect-Robust Memristor Accelerators without Re-Training
Rejina Maharjan and Chao Lu
Southern Illinois University Carbondale
13:35    Session 7A - 7A.3: RouteHD: A Routing-Aware FPGA Accelerator for HDC Classification
Abdullah Sahruri, Alaaddin Goktug Ayar, Sercan Aygun, Martin Margala
University of Louisiana at Lafayette
13:55    Session 7A - 7A.4: Multi-Stage Compression of Machine Learning Models
Nahyeon Kim and Prabhat Mishra
University of Florida
14:15    Session 7A - 7A.5: Early Class Exclusion in Hyperdimensional Computing
Rémy Duboucheix1, Mohsen Asghari1, Sébastien Le Beux1, Otmane Ait Mohamed1, Ron Mankarious2
1Concordia University, 2PolarSat Inc.
Friday April 10
                         Session 7B - System-Level and Supply-Chain Security for Trusted Computing
Chair: TBA, TBA
12:55    Session 7B - 7B.1: Security-Quality Scorecard: A Comprehensive Framework for Quantitative Evaluation of Quantitative Evaluation of Hardware-Enforced Boot Chain Security
Hyunmin Kim
TII
13:15    Session 7B - 7B.2: Proteus: A Morpheus II Extension for System-Level Moving-Target Defense and Key-Exposure Hardening
Jeremy Knickerbocker1, Syed Rafay Hasan2, Amr Hilal1, Mohammad Ashiqur Rahman3
1Tennessee Tech University, 2Tennessee Tech Univesity, 3Florida International University
13:35    Session 7B - 6B.3: A System-Level Design-Space Exploration of Security for Systems-on-Chip
Abigail Butka, Antonio Hendricks, Christophe Bobda
University of Florida
13:55    Session 7B - 6B.4: DUA: Detection of Unrecognized Applications Using One-Class SVM in NoC-Based SoCs
Andrea Galimberti1, Katsuaki Nakano2, Rohan Purkait2, Amlan Ganguly2, Michael Zuzak2, Mark A Indovina2, Sai Manoj Pudukotai Dinakarrao3, William Fornaciari1, Davide Zoni1
1Politecnico di Milano, 2Rochester Institute of Technology, 3George Mason University
14:15    Session 7B - 6B.5: Shadow Integrity Control (sic)
Amirreza Hashemi1, Hans Liljestrand2, Carlos Chinea Perez3, Jan-Erik Ekberg3
1Huawei Technologies/Aalto University, 2Huawei Technologies, Finland, 3Huawei Technologies
Friday April 10
                         Session 7C - EdgeAI and Applications
Chair: TBA, TBA